公开(公告)号：US20190042250A1

公开(公告)日：2019-02-07

申请号：US16003545

申请日：2018-06-08

Applicant: Intel Corporation

Inventor： Mark A. Anders ,  Himanshu Kaul ,  Sanu Mathew

IPC: G06F9/30 ,  G06F17/16 ,  G06N99/00

Abstract: Disclosed embodiments relate to a variable format, variable sparsity matrix multiplication (VFVSMM) instruction. In one example, a processor includes fetch and decode circuitry to fetch and decode a VFVSMM instruction specifying locations of A, B, and C matrices having (M×K), (K×N), and (M×N) elements, respectively, execution circuitry, responsive to the decoded VFVSMM instruction, to: route each row of the specified A matrix, staggering subsequent rows, into corresponding rows of a (M×N) processing array, and route each column of the specified B matrix, staggering subsequent columns, into corresponding columns of the processing array, wherein each of the processing units is to generate K products of A-matrix elements and matching B-matrix elements having a same row address as a column address of the A-matrix element, and to accumulate each generated product with a corresponding C-matrix element.

公开(公告)号：US09680459B2

公开(公告)日：2017-06-13

申请号：US14567987

申请日：2014-12-11

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul

IPC: H03L7/00 ,  H03K5/135 ,  G11C8/18 ,  G11C19/28 ,  G06F5/10 ,  H03K5/00

CPC classification number: H03K5/135 ,  G06F5/10 ,  G11C8/18 ,  G11C19/287 ,  H03K2005/00013

Abstract: A signal comprising a first edge and a second edge is received. The first edge of the signal is synchronized with a first clock and the synchronized first edge of the signal is passed to an output. The synchronization results in a delay of the first edge of the signal. The second edge of the signal is passed to the output. The passed second edge of the signal has a delay that is less than the delay of the first edge of the signal by at least one clock cycle of the first clock.

公开(公告)号：US20160380629A1

公开(公告)日：2016-12-29

申请号：US14751060

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul

IPC: H03K19/00 ,  H03K19/177

CPC classification number: H03K19/0008 ,  H03K19/17704 ,  H03K19/17744

Abstract: Described is an apparatus (e.g., a router) which comprises: multiple ports; and a plurality of crossbar circuits arranged such that at least one crossbar circuit receives all interconnects associated with a data bit of the multiple ports and is operable to re-route signals on those interconnects.

Abstract translation: 描述了一种装置（例如，路由器），其包括：多个端口; 以及布置成使得至少一个交叉电路接收与多个端口的数据位相关联的所有互连并且可操作以在那些互连上重新路由信号的多个交叉电路电路。

公开(公告)号：US20160182354A1

公开(公告)日：2016-06-23

申请号：US14579845

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Vivek K. De ,  Ram K. Krishnamurthy ,  Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul

IPC: H04L12/727 ,  H04L12/26 ,  H04L12/933

CPC classification number: H04L45/121 ,  G06F15/7825 ,  H04L43/0852 ,  H04L45/125 ,  H04L45/24 ,  H04L45/60 ,  H04L49/109

Abstract: A router of a network-on-chip receives delay information associated with a plurality of links of the network-on-chip. The router determines at least one link of a data path based on the delay information.

Abstract translation: 片上网络的路由器接收与片上网络的多个链路相关联的延迟信息。 路由器基于延迟信息确定数据路径的至少一个链路。

公开(公告)号：US20160182256A1

公开(公告)日：2016-06-23

申请号：US14574189

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Mark A. Anders ,  Himanshu Kaul ,  Gregory K. Chen

IPC: H04L12/64 ,  H04L12/50 ,  H04L12/66 ,  H04L12/24

CPC classification number: H04L12/64 ,  G06F15/7825 ,  H04L12/50 ,  H04L12/6418 ,  H04L12/66 ,  H04L41/02 ,  H04L49/109 ,  Y02D10/12 ,  Y02D10/13

Abstract: A packet-switched request from a first router of a network-on-chip is received. The packet-switched request is generated by source logic of the network-on-chip. Circuit-switched data associated with the packet switched request is also received. The circuit-switched data is stored by a storage element. The circuit-switched data is sent towards destination logic identified in the packet-switched request.

Abstract translation: 接收来自片上网络的第一路由器的分组交换请求。 分组交换请求由片上网络的源逻辑产生。 还接收与分组交换请求相关联的电路交换数据。 电路交换数据由存储元件存储。 电路交换数据被发送到分组交换请求中标识的目的地逻辑。

公开(公告)号：US09104474B2

公开(公告)日：2015-08-11

申请号：US13730390

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Sanu K. Mathew ,  Ram K. Krishnamurthy ,  William C. Hasenplaugh ,  Randy L. Allmon ,  Jonathan Enoch

IPC: G06F7/487 ,  G06F7/483 ,  G06F7/544

CPC classification number: G06F7/483 ,  G06F7/5443 ,  G06F9/30014 ,  G06F2207/382

Abstract: Embodiments of the present invention may provide methods and circuits for energy efficient floating point multiply and/or add operations. A variable precision floating point circuit may determine the certainty of the result of a multiply-add floating point calculation in parallel with the floating-point calculation. The variable precision floating point circuit may use the certainty of the inputs in combination with information from the computation, such as, binary digits that cancel, normalization shifts, and rounding, to perform a calculation of the certainty of the result. A floating point multiplication circuit may determine whether a lowest portion of a multiplication result could affect the final result and may induce a replay of the multiplication operation when it is determined that the result could affect the final result.

Abstract translation: 本发明的实施例可以提供用于节能浮点乘法和/或添加操作的方法和电路。 可变精度浮点电路可以与浮点计算并行地确定乘法加法浮点计算的结果的确定性。 可变精度浮点电路可以结合来自计算的信息，例如取消，归一化移位和舍入的二进制数字来使用输入的确定性来执行结果的确定性的计算。 浮点乘法电路可以确定乘法结果的最低部分是否可能影响最终结果，并且当确定结果可能影响最终结果时可以引起乘法运算的重放。