公开(公告)号：US20200096567A1

公开(公告)日：2020-03-26

申请号：US16141422

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Paul J. Diglio ,  Pooya Tadayon ,  Karumbu Meyyappan

IPC: G01R31/319 ,  G01R1/073

Abstract: Embodiments herein relate to a test probe. The test probe may have a first plurality of beams and a second plurality of beams. An intermediate substrate may be positioned between the first plurality of beams and the second plurality of beams. In embodiments, both the first and second plurality of beams may be angled. Other embodiments may be described or claimed.

公开(公告)号：US20200072871A1

公开(公告)日：2020-03-05

申请号：US16490517

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Pooya Tadayon ,  Joe F. Walczyk ,  Keith J. Marting

IPC: G01R1/073 ,  H05K1/11 ,  H05K3/42 ,  H05K3/00 ,  H05K3/40

Abstract: Space transformation technology for probe cards at sort is disclosed. In one example, a space transformer transforms a pitch of electrical contacts from a first distribution to a second distribution. The space transformer comprises a substrate with opposite first and second sides; and vias extending through the substrate between the first and second sides and oriented at different angles with respect to one another. In one example, a tester system or probe card for a die comprises a printed circuit board (PCB) with pads having a pad pitch; and a space transformer operatively coupled to the PCB, and having vias extending from the pads of the PCB through the space transformer at different angles with respect to one another and configured to electrically connect to contacts on the die having a contact pitch different than the pad pitch.

公开(公告)号：US20190212366A1

公开(公告)日：2019-07-11

申请号：US15863600

申请日：2018-01-05

Applicant: Intel Corporation

Inventor： Pooya Tadayon ,  Mark Bohr ,  Joe Walczyk

IPC: G01R1/073 ,  H01L23/48 ,  H01L23/32 ,  H01L23/14 ,  H01L21/48 ,  H01L21/027 ,  G01R31/28

CPC classification number: G01R1/07342 ,  G01R1/07378 ,  G01R31/2886 ,  H01L21/0273 ,  H01L21/486 ,  H01L23/147 ,  H01L23/32 ,  H01L23/481

Abstract: An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.

公开(公告)号：US20180252772A1

公开(公告)日：2018-09-06

申请号：US15447095

申请日：2017-03-01

Applicant: Intel Corporation

Inventor： Abram M. Detofsky ,  Evan M. Fledell ,  Mustapha A. Abdulai ,  John M. Peterson ,  Dinia P. Kitendaugh ,  Pooya Tadayon ,  Jin Pan ,  David Shia

IPC: G01R31/3185 ,  G01R31/28

CPC classification number: G01R31/31908 ,  G01R31/2886 ,  G01R31/31905

Abstract: A testing system and process comprises a converged test platform for structural testing and system testing of an integrated circuit device. The testing system comprises a converged test platform supported by a baseboard of an automated test assembly. The converged test platform comprises a DUT socket for testing an integrated circuit device, at least one testing electronic component selectively electrically coupled to the DUT socket by at least one switch operable to electrically switch at least some testing signals between the automated testing assembly and the DUT socket to the at least one testing electronic component for both structural testing and system testing of the integrated circuit device within the same test flow. The switch(es) and testing electronic component(s) (e.g., an FPGA) can be reprogrammable for testing flexibility and faster through put. Associated processes and methods are provided for both class and system testing using the converged test platform for back-end and front-end testing.

公开(公告)号：US12298572B2

公开(公告)日：2025-05-13

申请号：US17359183

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Changhua Liu ,  Pooya Tadayon ,  Zhichao Zhang ,  Liang Zhang ,  Srikant Nekkanty

IPC: G02B6/42

Abstract: Techniques and mechanisms for facilitating horizontal communication with a photonic integrated circuit (PIC) chip, and a lens structure which is optically coupled thereto. In an embodiment, a PIC chip comprises integrated circuitry, photonic waveguides, and integrated edge-oriented couplers (IECs) which are coupled to the integrated circuitry via the photonic waveguides. The PIC chip forms respective first divergent lens surfaces of the IECs, which are each at a respective terminus of a corresponding one of the photonic waveguides. A lens structure, which is adjacent to the IECs, comprises a second divergent lens surface having an orientation which is substantially orthogonal to the respective orientations of the first divergent lens surfaces. In another embodiment, an edge of the PIC chip forms one or more recess structures, and the lens structure comprises one or more tenon portions which each extends into a respective recess structure of the one or more recess structures.

公开(公告)号：US12272484B2

公开(公告)日：2025-04-08

申请号：US17192187

申请日：2021-03-04

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Pooya Tadayon ,  Kristof Darmawikarta ,  Tarek Ibrahim ,  Prithwish Chatterjee

IPC: H01F27/28 ,  H01F1/04 ,  H01F27/40 ,  H05K1/16

Abstract: An inductor can be formed in a coreless electronic substrate from magnetic materials and/or fabrication processes that do not result in the magnetic materials leaching into plating and/or etching solutions/chemistries, and results in a unique inductor structure. This may be achieved by forming the inductors from magnetic ferrites. The formation of the electronic substrates may also include process sequences that prevent exposure of the magnetic ferrites to the plating and/or etching solutions/chemistries.

公开(公告)号：US12213288B2

公开(公告)日：2025-01-28

申请号：US17134368

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Prabhakar Subrahmanyam ,  Arun Krishnamoorthy ,  Victor Polyanko ,  Ying-Feng Pang ,  Yi Xia ,  Pooya Tadayon ,  Muhammad Ahmad ,  Rahima K. Mohammed

IPC: H05K7/20

Abstract: An apparatus is described. The apparatus includes a liquid cooling system having multiple heat-exchangers and multiple valves. The multiple valves are to enable/disable participation of individual ones of the heat-exchangers within the liquid cooling system. The apparatus includes an information keeping device to store information that correlates a number of the multiple heat exchangers to be enabled to realize one or more semiconductor chips' target temperature for a power consumption of the one or more semiconductor chips for a plurality of combinations of target temperature and power consumption. The controller is coupled to the liquid cooling system and the information keeping device to dynamically determine during runtime of a system having the one or more semiconductor chips an appropriate number of the multiple heat exchangers to enable to realize a particular target temperature for the one or more semiconductor chips for a particular power consumption of the one or more semiconductor chips, and, update the information in the information keeping device with a new correlation that correlates the appropriate number with the particular target temperature and particular power consumption.

公开(公告)号：US12057370B2

公开(公告)日：2024-08-06

申请号：US17030137

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Paul Diglio ,  Pooya Tadayon ,  David Shia

IPC: H01L23/34 ,  C23C16/00 ,  H01L23/473

CPC classification number: H01L23/4735

Abstract: Embodiments disclosed herein include a temperature control system. In an embodiment, the temperature control system comprises a fluid reservoir for holding a fluid, and a spray chamber fluidically coupled to the fluid reservoir. In an embodiment, a pump is between the spray chamber and the fluid reservoir, where the pump provides the fluid to the spray chamber. In an embodiment, the temperature control system further comprises, a plurality of fluid lines between the pump and the spray chamber, where individual ones of the plurality of fluid lines are configured to provide the fluid to the spray chamber. In an embodiment, the temperature control system further comprises, a vacuum source fluidically coupled to the spray chamber, where the vacuum source controls a pressure within the spray chamber.

公开(公告)号：US12021016B2

公开(公告)日：2024-06-25

申请号：US16898196

申请日：2020-06-10

Applicant: Intel Corporation

Inventor： Chandra Mohan Jha ,  Pooya Tadayon ,  Aastha Uppal ,  Weihua Tang ,  Paul Diglio ,  Xavier Brun

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/78 ,  H01L23/373 ,  H01L23/522

CPC classification number: H01L23/49833 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3732 ,  H01L23/3738 ,  H01L23/5226

Abstract: Embodiments disclosed herein comprise a die and methods of forming a die. In an embodiment, a die comprises, a die substrate, wherein the die substrate has a first thermal conductivity, and a first layer over the die substrate, wherein the first layer has a second thermal conductivity that is greater than the first thermal conductivity. In an embodiment, the die further comprises a second layer over the first layer, wherein the second layer comprises transistors.

公开(公告)号：US11984430B2

公开(公告)日：2024-05-14

申请号：US18128958

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Mark T. Bohr ,  Wilfred Gomes ,  Rajesh Kumar ,  Pooya Tadayon ,  Doug Ingerly

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/13 ,  H01L2225/06541

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.