公开(公告)号：US11676889B2

公开(公告)日：2023-06-13

申请号：US17573479

申请日：2022-01-11

Applicant: Intel Corporation

Inventor： Arnab Sarkar ,  Sujit Sharan ,  Dae-Woo Kim

IPC: H01L23/498 ,  H01L23/544 ,  H01L21/66 ,  H01L23/58 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/49827 ,  H01L22/32 ,  H01L23/544 ,  H01L23/585 ,  H01L24/10 ,  H01L25/0655 ,  H01L24/16 ,  H01L25/18 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/14 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1517 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/3512

Abstract: Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure incudes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.

公开(公告)号：US20230016326A1

公开(公告)日：2023-01-19

申请号：US17956761

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Henning M. Braunisch ,  Chia-Pin Chiu ,  Aleksander Aleksov ,  Hinmeng AU ,  Stefanie M. LOTZ ,  Johanna M. Swan ,  Sujit Sharan

IPC: H01L23/538 ,  H01L23/13 ,  H01L23/00 ,  H01L25/065

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

公开(公告)号：US11387187B2

公开(公告)日：2022-07-12

申请号：US16021966

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Andrew Paul Collins ,  Jianyong Xie ,  Sujit Sharan ,  Henning Braunisch ,  Aleksandar Aleksov

IPC: H01L23/495 ,  H01L23/053 ,  H01L23/48 ,  H01L21/4763 ,  H01L23/538 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L25/07

Abstract: Embodiments may relate to an interposer that has a first layer with a plurality of first layer pads that may couple with a die. The interposer may further include a second layer with a power delivery component. The interposer may further include a very high density (VHD) layer, that has a VHD pad coupled by a first via with the power delivery component and coupled by a second via with a first layer pad. Other embodiments may be described and/or claimed.

公开(公告)号：US11222847B2

公开(公告)日：2022-01-11

申请号：US16469084

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Ravindranath V. Mahajan ,  Zhiguo Qian ,  Henning Braunisch ,  Kemal Aygun ,  Sujit Sharan

IPC: H01L23/538 ,  H01L25/065

Abstract: A device and method of utilizing a repeater circuit to extend the viable length of an interconnect bridge. Integrated circuit packages using a repeater circuit in a repeater die, embedded in a substrate, and included in an interconnect bridge are show. Methods of connecting semiconductor dies using interconnect bridges coupled with repeater circuits are shown.

公开(公告)号：US20200235048A1

公开(公告)日：2020-07-23

申请号：US16838556

申请日：2020-04-02

Applicant: Intel Corporation

Inventor： Andrew Collins ,  Jianyong Xie ,  Sujit Sharan

IPC: H01L23/498 ,  H01L25/16 ,  H01L23/42 ,  H01L49/02 ,  H01L21/48

Abstract: A micro-trace containing package substrate provides a low-inductance alternating-current decoupling path between a semiconductive device and a die-side capacitor.

公开(公告)号：US10418312B2

公开(公告)日：2019-09-17

申请号：US15749465

申请日：2015-10-29

Applicant: Intel Corporation

Inventor： Arnab Sarkar ,  Sujit Sharan ,  Dae-Woo Kim

IPC: H01L23/498 ,  H01L23/544 ,  H01L21/66 ,  H01L23/58 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18

Abstract: Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.

公开(公告)号：US20190157232A1

公开(公告)日：2019-05-23

申请号：US16320680

申请日：2016-08-16

Applicant: Intel Corporation

Inventor： Dae-Wood Kim ,  Ajay Jain ,  Neha M. Patel ,  Rodrick J. Hendricks ,  Sujit Sharan

IPC: H01L23/00

CPC classification number: H01L24/16 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/562 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15192 ,  H01L2924/3512

Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.

公开(公告)号：US12243812B2

公开(公告)日：2025-03-04

申请号：US18386913

申请日：2023-11-03

Applicant: Intel Corporation

Inventor： Dae-Woo Kim ,  Sujit Sharan

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L25/065 ,  H01L23/48

Abstract: Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.

公开(公告)号：US12057413B2

公开(公告)日：2024-08-06

申请号：US16393047

申请日：2019-04-24

Applicant: Intel Corporation

Inventor： Lijiang Wang ,  Jianyong Xie ,  Arghya Sain ,  Xiaohong Jiang ,  Sujit Sharan ,  Kemal Aygun

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/66 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2223/6638 ,  H01L2224/16225 ,  H01L2924/30111

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first trace embedded in a package substrate. In an embodiment, the first trace comprises a first region, where the first region has a first width, and a second region, where the second region has a second width that is smaller than the first width.

公开(公告)号：US20240006286A1

公开(公告)日：2024-01-04

申请号：US17856795

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Arghya Sain ,  Sujit Sharan ,  Hoai V. Le ,  Jianyong Xie

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/49827 ,  H01L23/15 ,  H01L24/16 ,  H01L2224/16235

Abstract: A substrate comprising a core structure between a first metallization stack and a second metallization stack. A hardware interface is at a side of the second metallization stack. A first interconnect comprises both a first via portion, and a first trace portion which extends from the first via portion in a first routing layer of the first metallization stack. The first via portion extends from the hardware interface, through both the second metallization stack and the core structure, to the first routing layer. A second interconnect comprises both a second via portion, and a second trace portion which extends from the second via portion in the first routing layer. The second via portion extends from the hardware interface, through both the second metallization stack and the core structure, to the first routing layer. A first multi-layer insulator structure adjoins respective sides of the first and second trace portions.