公开(公告)号：US20180307984A1

公开(公告)日：2018-10-25

申请号：US15494971

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Altug Koker ,  Abhishek R. Appu ,  Kamal Sinha ,  Joydeep Ray ,  Balaji Vembu ,  Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  John C. Weast ,  Justin E. Gottschlich ,  Prasoonkumar Surti ,  Chandrasekaran Sakthivel ,  Farshad Akhbari ,  Nadathur Rajagopalan Satish ,  Liwei Ma ,  Jeremy Bottleson ,  Eriko Nurvitadhi ,  Travis T. Schluessler ,  Ankur N. Shah ,  Jonathan Kennedy ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: G06N3/08 ,  G06N99/00

CPC classification number: G06N3/08 ,  G06F9/28 ,  G06F9/505 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/0481 ,  G06N3/063 ,  G06N99/005

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180300130A1

公开(公告)日：2018-10-18

申请号：US15488929

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Kiran C Veernapu ,  Balaji Vembu ,  Vasanth Ranganathan ,  Prasoonkumar Surti

IPC: G06F9/30 ,  G06F12/0846 ,  G06F9/54 ,  G06F13/42 ,  G06F13/40 ,  G06T1/20

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to monitor a thread switching overhead parameter for an application executing in a processing system and in response to a determination that the thread switching overhead parameter exceeds a threshold, to activate a thread management algorithm to reduce thread switching in the processing system. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180293102A1

公开(公告)日：2018-10-11

申请号：US15482801

申请日：2017-04-09

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Balaji Vembu ,  Rajkishore Barik ,  Eriko Nurvitadhi ,  Nicolas C. Galoppo Von Borries ,  Tsung-Han Lin ,  Sanjeev Jahagirdar ,  Vasanth Ranganathan

IPC: G06F9/50 ,  G06T1/20 ,  G06F9/52 ,  G06F9/48

Abstract: A mechanism is described for facilitating intelligent thread scheduling at autonomous machines. A method of embodiments, as described herein, includes detecting dependency information relating to a plurality of threads corresponding to a plurality of workloads associated with tasks relating to a processor including a graphics processor. The method may further include generating a tree of thread groups based on the dependency information, where each thread group includes multiple threads, and scheduling one or more of the thread groups associated a similar dependency to avoid dependency conflicts.

公开(公告)号：US20160086374A1

公开(公告)日：2016-03-24

申请号：US14492173

申请日：2014-09-22

Applicant: Intel Corporation

Inventor： Robert L. Farrell ,  Prasoonkumar Surti ,  Vasanth Ranganathan ,  Karol A. Szerszen

IPC: G06T15/40 ,  G06T9/00 ,  G06T5/00

CPC classification number: G06T15/405 ,  G06T5/002 ,  G06T9/00 ,  G06T11/40

Abstract: By packing the depth data in a way that is independent of the number of samples, so that memory bandwidth is the same regardless of the number of samples, higher numbers of samples per pixel may be used without adversely affecting buffer cost. In some embodiments, the number of pixels per clock in a first level depth test may be increased by operating in the pixel domain, whereas previous solutions operated at the sample level.

Abstract translation: 通过以独立于样本数量的方式打包深度数据，使得存储器带宽相同，而不考虑样本数量，可以使用每像素更多的采样数，而不会不利地影响缓冲器成本。 在一些实施例中，可以通过在像素域中操作来增加第一级深度测试中每个时钟的像素数量，而先前的解决方案在采样级别下运行。

公开(公告)号：US20250166114A1

公开(公告)日：2025-05-22

申请号：US18967123

申请日：2024-12-03

Applicant: Intel Corporation

Inventor： Abhishek Appu ,  Subramaniam Maiyuran ,  Mike Macpherson ,  Fangwen Fu ,  Jiasheng Chen ,  Varghese George ,  Vasanth Ranganathan ,  Ashutosh Garg ,  Joydeep Ray

IPC: G06T1/20 ,  G06F7/544 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/0806 ,  G06F15/80 ,  G06F17/16 ,  G06N3/048 ,  G06N3/08 ,  G06N3/084

Abstract: Embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides for data aware sparsity via compressed bitstreams. One embodiment provides for block sparse dot product instructions. One embodiment provides for a depth-wise adapter for a systolic array.

公开(公告)号：US20250156371A1

公开(公告)日：2025-05-15

申请号：US19014672

申请日：2025-01-09

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Aravindh Anantaraman ,  Elmoustapha Ould-Ahmed-Vall ,  Valentin Andrei ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Altug Koker ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Joydeep Ray ,  Vasanth Ranganathan

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/06 ,  H03M7/46

Abstract: Methods and apparatus relating to data initialization techniques. In an example, an apparatus comprises a processor to read one or more metadata codes which map to one or more cache lines in a cache memory and invoke a random number generator to generate random numerical data for the one or more cache lines in response to a determination that the one more metadata codes indicate that the cache lines are to contain random numerical data. Other embodiments are also disclosed and claimed.

公开(公告)号：US20250117356A1

公开(公告)日：2025-04-10

申请号：US18915492

申请日：2024-10-15

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Aravindh Anantaraman ,  Elmoustapha Ould-Ahmed-Vall ,  Valentin Andrei ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Joydeep Ray ,  Lakshminarayanan Striramassarma ,  Scott Janus ,  Brent Insko ,  Vasanth Ranganathan ,  Kamal Sinha ,  Arthur Hunter ,  Prasoonkumar Surti ,  David Puffer ,  James Valerio ,  Ankur N. Shah

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/06 ,  H03M7/46

Abstract: Methods and apparatus relating to techniques for multi-tile memory management. In an example, a graphics processor includes an interposer, a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource, cache circuitry coupled with the graphics processing resource via the interconnect network, and a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache. The memory controller is configured to enable access to a high-bandwidth memory (HBM) device, the memory-side cache is configured to cache data associated with a memory access performed via the memory controller, and the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface.

公开(公告)号：US12217053B2

公开(公告)日：2025-02-04

申请号：US18528340

申请日：2023-12-04

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Sanu K. Mathew ,  Anbang Yao ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Rajkishore Barik ,  Tsung-Han Lin ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: G06F9/30 ,  G06F7/483 ,  G06F7/544 ,  G06F9/38 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08 ,  G09G5/393 ,  G06F1/16 ,  G06F17/16 ,  G06N20/00 ,  G06T15/00

Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute an intermediate product of 16-bit operands and to compute a 32-bit sum based on the intermediate product.

公开(公告)号：US20240411717A1

公开(公告)日：2024-12-12

申请号：US18738785

申请日：2024-06-10

Applicant: Intel Corporation

Inventor： Altug Koker ,  Lakshminarayanan Striramassarma ,  Aravindh Anantaraman ,  Valentin Andrei ,  Abhishek R. Appu ,  Sean Coleman ,  Varghese George ,  Pattabhiraman K ,  Mike MacPherson ,  Subramaniam Maiyuran ,  ElMoustapha Ould-Ahmed-Vall ,  Vasanth Ranganathan ,  Joydeep Ray ,  Jayakrishna P S ,  Prasoonkumar Surti

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/06 ,  H03M7/46

Abstract: Embodiments are generally directed to cache structure and utilization. An embodiment of an apparatus includes one or more processors including a graphics processor; a memory for storage of data for processing by the one or more processors; and a cache to cache data from the memory; wherein the apparatus is to provide for dynamic overfetching of cache lines for the cache, including receiving a read request and accessing the cache for the requested data, and upon a miss in the cache, overfetching data from memory or a higher level cache in addition to fetching the requested data, wherein the overfetching of data is based at least in part on a current overfetch boundary, and provides for data is to be prefetched extending to the current overfetch boundary.

公开(公告)号：US20240403259A1

公开(公告)日：2024-12-05

申请号：US18779461

申请日：2024-07-22

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Aravindh Anantaraman ,  Elmoustapha Ould-Ahmed-Vall ,  Joydeep Ray ,  Mike MacPherson ,  Valentin Andrei ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Subramaniam Maiyuran ,  Vasanth Ranganathan ,  Jayakrishna P S ,  Pattabhiraman K ,  Sudhakar Kamma

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/06 ,  H03M7/46

Abstract: Methods and apparatus relating to techniques for data compression. In an example, an apparatus comprises a processor receive a data compression instruction for a memory segment; and in response to the data compression instruction, compress a sequence of identical memory values in response to a determination that the sequence of identical memory values has a length which exceeds a threshold. Other embodiments are also disclosed and claimed.