公开(公告)号：US20190179560A1

公开(公告)日：2019-06-13

申请号：US15837685

申请日：2017-12-11

Applicant: Micron Technology, Inc.

Inventor： Byung S. Moon ,  Harish N. Venkata ,  Gary L. Howe ,  Myung Ho Bae

IPC: G06F3/06 ,  G11C11/4072

CPC classification number: G06F3/0652 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/0685 ,  G06F11/1048 ,  G06F11/1068 ,  G11C7/1018 ,  G11C7/20 ,  G11C8/04 ,  G11C11/4072 ,  G11C29/022 ,  G11C29/028 ,  G11C29/46 ,  G11C29/52

Abstract: A memory device may include a memory array that includes multiple memory cells. The memory device may also include multiple sense amplifiers that, in operation, may each be connected to one or more memory cells. The sense amplifiers may be designed to assist in writing logical zeros to the multiple memory cells.

公开(公告)号：US20190161341A1

公开(公告)日：2019-05-30

申请号：US15824559

申请日：2017-11-28

Applicant: Micron Technology, Inc.

Inventor： Gary L. Howe

IPC: B81B7/00 ,  G11C11/56 ,  B81C1/00

Abstract: A memory device may include a memory array including a plurality of memory cells and a die stack including at least a portion of the plurality of memory cells. The memory device may also include multiple temperature sensors each designed to output a temperature code corresponding to the temperature of a respective die of the die stack. One die of the die stack is then designed to output the temperature code corresponding to the hottest die of the die stack.

公开(公告)号：US20170371539A1

公开(公告)日：2017-12-28

申请号：US15189900

申请日：2016-06-22

Applicant: Micron Technology, Inc.

Inventor： Thanh K. Mai ,  Gary L. Howe ,  Daniel B. Penney

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0625 ,  G06F3/0646 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/161 ,  G11C8/00 ,  Y02D10/14

Abstract: The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.

公开(公告)号：US12087394B2

公开(公告)日：2024-09-10

申请号：US17930655

申请日：2022-09-08

Applicant: Micron Technology, Inc.

Inventor： Brian W. Huber ,  Scott E. Smith ,  Gary L. Howe

IPC: G11C7/10

CPC classification number: G11C7/1084 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/1096

Abstract: A memory device includes a command interface configured to receive write commands from a host device. Additionally, the memory device includes an input buffer configured to buffer a strobe signal from the host device. Furthermore, the memory device includes a first ripple counter and a second ripple counter. The memory device includes command handling circuitry configured to alternatingly start the first ripple counter and the second ripple counter in response to consecutive write commands. The command handling circuitry and/or the first and second ripple counters are configured to suppress a reset of the input buffer if either the first ripple counter or the second ripple counter has not reached a threshold and is still counting.

公开(公告)号：US20240087621A1

公开(公告)日：2024-03-14

申请号：US17930655

申请日：2022-09-08

Applicant: Micron Technology, Inc.

Inventor： Brian W. Huber ,  Scott E. Smith ,  Gary L. Howe

IPC: G11C7/10

CPC classification number: G11C7/1084 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/1096

Abstract: A memory device includes a command interface configured to receive write commands from a host device. Additionally, the memory device includes an input buffer configured to buffer a strobe signal from the host device. Furthermore, the memory device includes a first ripple counter and a second ripple counter. The memory device includes command handling circuitry configured to alternatingly start the first ripple counter and the second ripple counter in response to consecutive write commands. The command handling circuitry and/or the first and second ripple counters are configured to suppress a reset of the input buffer if either the first ripple counter or the second ripple counter has not reached a threshold and is still counting.

公开(公告)号：US11462254B2

公开(公告)日：2022-10-04

申请号：US17094731

申请日：2020-11-10

Applicant: Micron Technology, Inc.

Inventor： Gary L. Howe ,  Miles S. Wiscombe ,  James S. Rehmeyer ,  Eric J. Stave

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/4074 ,  G11C5/14

Abstract: Methods, apparatuses, and systems related to voltage management of memory apparatuses/systems are described. The memory device can include circuitry configured to determine an operating frequency of a clock signal for an ongoing or an upcoming memory operation. The memory device may generate a control indicator for increasing a system voltage for higher operating frequencies, for decreasing the system voltage for lower operating frequencies, or a combination thereof.

公开(公告)号：US11430504B2

公开(公告)日：2022-08-30

申请号：US17005034

申请日：2020-08-27

Applicant: Micron Technology, Inc.

Inventor： Miles S. Wiscombe ,  Scott E. Smith ,  Gary L. Howe ,  Brian W. Huber ,  Tony M. Brewer

IPC: G06F13/28 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/406 ,  G11C11/4094

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to provide row clear features. In some embodiments, the memory device may receive a command from a host device directed to a row of a memory array included in the memory device. The memory device may determine that the command is directed to two or more columns associated with the row, where each column is coupled with a group of memory cells. The memory device may activate the row to write the two or more columns using a set of predetermined data stored in a register of the memory device. Subsequently, the memory device may deactivate the word line based on writing the set of predetermined data to the two or more columns.

公开(公告)号：US11409674B2

公开(公告)日：2022-08-09

申请号：US17062484

申请日：2020-10-02

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Vaughn N. Johnson ,  Kyle Alexander ,  Gary L. Howe ,  Brian T. Pecha ,  Miles S. Wiscombe

IPC: G06F13/16 ,  G11C11/406 ,  G11C11/4096

Abstract: Memory devices and systems with improved command/address bus utilization are disclosed herein. In one embodiment, a memory device comprises a plurality of external command/address terminals and a command decoder. The plurality of external command/address terminals are configured to receive a command as a corresponding plurality of command/address bits. A first set of the command/address bits indicate a read or write operation. A second set of the command/address bits indicate whether to execute a refresh operation. The memory device is configured to, in response to the first set of command/address bits, execute the read or write operation on a portion of a memory array. The memory device is further configured to, in response to the second set of command/address bits, execute the refresh operation to refresh at least one memory bank of the memory array when the second set of command/address bits indicate that the refresh operation should be executed.

公开(公告)号：US11182085B2

公开(公告)日：2021-11-23

申请号：US16555293

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/06

Abstract: Apparatuses and methods for memory array accessibility can include an apparatus with an array of memory cells. The array can include a first portion accessible by a controller of the array and inaccessible to devices external to the apparatus. The array can include a second portion accessible to the devices external to the apparatus. The array can include a number of registers that store row address that indicate which portion of the array is the first portion. The apparatus can include the controller configured to access the number of registers to allow access to the second portion by the devices external to the apparatus based on the stored row addresses.

公开(公告)号：US11139008B2

公开(公告)日：2021-10-05

申请号：US16779866

申请日：2020-02-03

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/4093

Abstract: A memory device includes a command interface configured to receive a write command and internal write adjust (IWA) circuitry. The IWA circuitry is configured to receive the write command from the command interface, generate an internal write signal (IWS) based upon the received write command and train a data strobe (DQS) signal to generate a DQS signal having a set amount of phase alignment with a clock (CLK) of the memory device to capture a data signal (DQ) using the IWS.