公开(公告)号：US12019780B2

公开(公告)日：2024-06-25

申请号：US18099071

申请日：2023-01-19

Applicant: Micron Technology, Inc.

Inventor： Tomoko Ogura Iwasaki ,  Manik Advani ,  Samir Mittal

IPC: G06F21/62 ,  G06F12/10

CPC classification number: G06F21/6227 ,  G06F12/10 ,  G06F2212/1052

Abstract: An access request is received. The access request comprises a physical page address corresponding to a primary memory block of a memory device, an input security key, and a logical page address corresponding to the physical page address. The input security key is provided as input to a (CAM) block that stores a plurality of security keys to verify that the input security key matches a stored security key. A location of the stored security key is checked to verify that it corresponds to the logical page address included in the access request based a predetermined mapping. Based on verifying that the stored security key corresponds to the logical page address included in the access request, the physical page address corresponding to the primary memory block is accessed.

公开(公告)号：US11836380B2

公开(公告)日：2023-12-05

申请号：US17304522

申请日：2021-06-22

Applicant: Micron Technology, Inc.

Inventor： Parag R. Maharana ,  Anirban Ray ,  Gurpreet Anand ,  Samir Rajadnya ,  Paul Stonelake ,  Samir Mittal

IPC: G06F3/06 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0622 ,  G06F3/0688 ,  G06F13/1668 ,  G06F13/4282 ,  G06F2213/0024

Abstract: A processing device, operatively coupled with one or more memory devices, is configured to provide a plurality of virtual memory controllers, partition one or more memory devices into a plurality of physical partitions, and associate each of the plurality of virtual memory controllers with one of the plurality of physical partitions. The processing device further provides a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers, and presents the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface.

公开(公告)号：US11669260B2

公开(公告)日：2023-06-06

申请号：US17729738

申请日：2022-04-26

Applicant: Micron Technology, Inc.

Inventor： Samir Mittal ,  Anirban Ray ,  Gurpreet Anand

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0811 ,  G06F13/16 ,  G06N3/08

CPC classification number: G06F3/0646 ,  G06F3/061 ,  G06F3/068 ,  G06F3/0658 ,  G06F12/0811 ,  G06F13/1694 ,  G06N3/08 ,  G06F2212/1021

Abstract: A computing system having memory components of different tiers. The computing system further includes a controller, operatively coupled between a processing device and the memory components, to: receive from the processing device first data access requests that cause first data movements across the tiers in the memory components; service the first data access requests after the first data movements; predict, by applying data usage information received from the processing device in a prediction model trained via machine learning, second data movements across the tiers in the memory components; and perform the second data movements before receiving second data access requests, where the second data movements reduce third data movements across the tiers caused by the second data access requests.

公开(公告)号：US20230161896A1

公开(公告)日：2023-05-25

申请号：US18099071

申请日：2023-01-19

Applicant: Micron Technology, Inc.

Inventor： Tomoko Ogura Iwasaki ,  Manik Advani ,  Samir Mittal

IPC: G06F21/62 ,  G06F12/10

CPC classification number: G06F21/6227 ,  G06F12/10 ,  G06F2212/1052

Abstract: An access request is received. The access request comprises a physical page address corresponding to a primary memory block of a memory device, an input security key, and a logical page address corresponding to the physical page address. The input security key is provided as input to a (CAM) block that stores a plurality of security keys to verify that the input security key matches a stored security key. A location of the stored security key is checked to verify that it corresponds to the logical page address included in the access request based a predetermined mapping. Based on verifying that the stored security key corresponds to the logical page address included in the access request, the physical page address corresponding to the primary memory block is accessed.

公开(公告)号：US11630594B2

公开(公告)日：2023-04-18

申请号：US17471841

申请日：2021-09-10

Applicant: Micron Technology, Inc.

Inventor： Anirban Ray ,  Samir Mittal ,  Gurpreet Anand

IPC: G06F3/06 ,  G06F16/901 ,  G06N7/00 ,  G06F12/0862 ,  G06F12/02

Abstract: A graph can be generated based on an access pattern associated with blocks of a memory device that have been accessed by a host system, wherein the graph comprises nodes representing at least a subset of the blocks that have been accessed by the host system and edges that are based on the access pattern, wherein each edge is associated with a respective probability value between a respective pair of nodes. A number of edges having respective probability values that satisfy a probability value threshold criterion can be determined. It can be determined whether the number of edges satisfies a decayed edge value condition. In response to determining that the number of edges does not satisfy the decayed edge value condition, the graph can be removed.

公开(公告)号：US11354056B2

公开(公告)日：2022-06-07

申请号：US16905834

申请日：2020-06-18

Applicant: Micron Technology, Inc.

Inventor： Samir Mittal ,  Anirban Ray ,  Gurpreet Anand

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0811 ,  G06F13/16 ,  G06N3/08

Abstract: A computing system having memory components of different tiers. The computing system further includes a controller, operatively coupled between a processing device and the memory components, to: receive from the processing device first data access requests that cause first data movements across the tiers in the memory components; service the first data access requests after the first data movements; predict, by applying data usage information received from the processing device in a prediction model trained via machine learning, second data movements across the tiers in the memory components; and perform the second data movements before receiving second data access requests, where the second data movements reduce third data movements across the tiers caused by the second data access requests.

公开(公告)号：US20210349638A1

公开(公告)日：2021-11-11

申请号：US17382200

申请日：2021-07-21

Applicant: Micron Technology, Inc.

Inventor： Parag R. Maharana ,  Anirban Ray ,  Gurpreet Anand ,  Samir Mittal

IPC: G06F3/06 ,  H04L29/08 ,  G11C14/00 ,  G06F13/28 ,  G06F15/173 ,  G06F12/00

Abstract: A memory system having memory components, a remote direct memory access (RDMA) network interface card (RNIC), and a host system, and configured to: allocate a page of virtual memory for an application; map the page of virtual memory to a page of physical memory in the memory components; instruct the RNIC to perform an RDMA operation; perform, during the RDMA operation, a data transfer between the page of physical memory in the plurality of memory components and a remote device that is connected via a computer network to the remote direct memory access network interface card; and at least for a duration of the data transfer, lock a mapping between the page of virtual memory and the page of physical memory in the memory components.

公开(公告)号：US20210200889A1

公开(公告)日：2021-07-01

申请号：US16727682

申请日：2019-12-26

Applicant: Micron Technology, Inc.

Inventor： Tomoko Ogura Iwasaki ,  Manik Advani ,  Samir Mittal

IPC: G06F21/62 ,  G06F12/10

Abstract: An access request is received. The access request comprises a physical page address corresponding to a primary memory block of a memory device, an input security key, and a logical page address corresponding to the physical page address. The input security key is provided as input to a (CAM) block that stores a plurality of security keys to verify that the input security key matches a stored security key. A location of the stored security key is checked to verify that it corresponds to the logical page address included in the access request based a predetermined mapping. Based on verifying that the stored security key corresponds to the logical page address included in the access request, the physical page address corresponding to the primary memory block is accessed.

公开(公告)号：US20210117326A1

公开(公告)日：2021-04-22

申请号：US17135207

申请日：2020-12-28

Applicant: Micron Technology, Inc.

Inventor： Anirban Ray ,  Samir Mittal ,  Gurpreet Anand ,  Parag R. Maharana

IPC: G06F12/0862 ,  G06F12/1009 ,  G06F12/0871 ,  G06F12/0873 ,  G06N3/08 ,  G06F9/455

Abstract: A computing system having memory components, including first memory and second memory. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, in a prediction engine, usage history of pages in the second memory; train a prediction model based on the usage history; predict, by the prediction engine using the prediction model, likelihood of the pages being used in a subsequent period of time; and responsive to the likelihood predicted by the prediction engine, copy by a controller data in a page in the second memory to the first memory.

公开(公告)号：US20210049101A1

公开(公告)日：2021-02-18

申请号：US16539139

申请日：2019-08-13

Applicant: Micron Technology, Inc.

Inventor： Anirban Ray ,  Paul Stonelake ,  Samir Mittal ,  Gurpreet Anand

IPC: G06F12/0868 ,  G06F13/28 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42

Abstract: A processing device in a host system monitors a data temperature of a plurality of memory pages stored in a host-addressable region of a cache memory component operatively coupled with the host system. The processing device determines that a first memory page of the plurality of memory pages satisfies a first threshold criterion pertaining to the data temperature of the first memory page and sends a first migration command indicating the first memory page to a direct memory access (DMA) engine executing on a memory-mapped storage component operatively coupled with the cache memory component and with the memory-mapped storage component via a peripheral component interconnect express (PCIe) bus. The first migration command causes the DMA engine to initiate a first DMA transfer of the first memory page from the cache memory component to a host-addressable region of the memory-mapped storage component.