公开(公告)号：US20210398997A1

公开(公告)日：2021-12-23

申请号：US16908287

申请日：2020-06-22

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Justin B. Dorhout

IPC: H01L27/11556 ,  H01L23/00 ,  G11C5/02 ,  G11C5/06 ,  H01L21/768 ,  H01L27/11582 ,  H01L23/538

Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, the tiers individually comprising one of the conductive structures and one of the insulative structures, first support pillar structures extending through the stack structure within a first region of the microelectronic device, the first support pillar structures electrically isolated from a source structure underlying the stack structure, second support pillar structures extending through the stack structure within a second region of the microelectronic device, the second support pillar structures comprising an electrically conductive material in electrical communication with the source structure, and bridge structures extending between at least some neighboring first support pillar structures of the first support pillar structures. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20210375907A1

公开(公告)日：2021-12-02

申请号：US16885720

申请日：2020-05-28

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: Some embodiments include an integrated assembly having a first deck, a second deck over the first deck, and a third deck over the second deck. The first deck has first conductive levels disposed one atop another. The second deck has second conductive levels disposed one atop another. The third deck has third conductive levels disposed one atop another. A first staircase region extends to the first and second conductive levels, and passes through the third conductive levels. A second staircase region extends to the third conductive levels and not to the first and second conductive levels. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210280597A1

公开(公告)日：2021-09-09

申请号：US16811118

申请日：2020-03-06

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02 ,  G11C5/06

Abstract: Some embodiments include an integrated assembly having a memory array region which includes channel material pillars extending through a stack of alternating conductive and insulative levels. A second region is adjacent the memory array region. A conductive expanse is within the memory array region and electrically coupled with the channel material of the channel material pillars. A panel extends across the memory array region and the second region. The panel separates one memory block region from another. The panel has a first portion over the conductive expanse, and has a second portion adjacent the first portion. The panel has a bottom surface. A first segment of the bottom surface is adjacent an upper surface of the conductive expanse. A segment of the bottom surface within the second portion is elevationally offset relative to the first segment. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210126010A1

公开(公告)日：2021-04-29

申请号：US16667719

申请日：2019-10-29

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Justin B. Dorhout

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  G11C16/08

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure. The microelectronic device structure comprises a stack structure comprising insulative structures and additional insulative structures vertically alternating with the insulative structures, a dielectric structure vertically extending partially through the stack structure, and a dielectric material vertically overlying and horizontally extending across the stack structure and the dielectric structure. Portions of at least the dielectric material and the dielectric structure are removed to form a trench vertically overlying and at least partially horizontally overlapping a remaining portion of the dielectric structure. The trench is substantially filled with additional dielectric material. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20210126009A1

公开(公告)日：2021-04-29

申请号：US16667704

申请日：2019-10-29

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Xuan Li ,  Adeline Yii

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556

Abstract: A microelectronic device comprises a stack structure, at least one staircase structure, contact structures, and support structures. The stack structure comprises vertically alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures. The at least one staircase structure is within the stack structure and has steps comprising edges of at least some of the tiers. The contact structures are on the steps of the at least one staircase structure. The support structures horizontally alternate with the contact structures in a first horizontal direction and vertically extend through the stack structure. The support structures have oblong horizontal cross-sectional shapes. Additional microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20250098158A1

公开(公告)日：2025-03-20

申请号：US18966674

申请日：2024-12-03

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Brett D. Lowe

IPC: H10B41/27 ,  G11C5/02 ,  G11C5/06 ,  H01L23/528 ,  H10B43/27

Abstract: A microelectronic device comprises a stack structure, slot structures vertically extending completely through the stack structure, and support pillar structures vertically extending through the stack structure. The stack structure comprises tiers vertically stacked relative to one another, each tier including a conductive material and insulative material vertically neighboring the conductive material. The stack structure includes a staircase structure therein comprising steps defined by edges of at least some of the tiers. The support pillar structures are arranged in rows horizontally extending in a first direction. The slot structures divide the stack structure into block structures. The microelectronic device further comprises additional slot structures within a horizontal area of one of the block structures. The additional slot structures include a first additional slot structure at least partially intersecting one of the rows of the support pillar structures. The additional slot structures also include a second additional slot structure horizontally spaced apart from the first additional slot structure and each of the rows of the support pillar structures in a second direction orthogonal to the first direction.

公开(公告)号：US20250056802A1

公开(公告)日：2025-02-13

申请号：US18930589

申请日：2024-10-29

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Dong Wang ,  Rui Zhang ,  Da Xing ,  Xiao Li ,  Pei Qiong Cheung ,  Xiao Zeng

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/40 ,  H10B43/40

Abstract: Some embodiments include an assembly having conductive structures distributed along a level within a memory array region and another region proximate the memory array region. The conductive structures include a first stack over a metal-containing region. A semiconductor material is within the first stack. A second stack is over the conductive structures, and includes alternating conductive tiers and insulative tiers. Cell-material-pillars are within the memory array region. The cell-material-pillars include channel material. The semiconductor material directly contacts the channel material. Conductive post structures are within the other region. Some of the conductive post structures are dummy structures and have bottom surfaces which are entirely along an insulative oxide material. Others of the conductive post structures are live posts electrically coupled with CMOS circuitry. Some embodiments include methods of forming assemblies.

公开(公告)号：US12167604B2

公开(公告)日：2024-12-10

申请号：US18381791

申请日：2023-10-19

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Dong Wang ,  Rui Zhang ,  Da Xing ,  Xiao Li ,  Pei Qiong Cheung ,  Xiao Zeng

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/40 ,  H10B43/40

Abstract: Some embodiments include an assembly having conductive structures distributed along a level within a memory array region and another region proximate the memory array region. The conductive structures include a first stack over a metal-containing region. A semiconductor material is within the first stack. A second stack is over the conductive structures, and includes alternating conductive tiers and insulative tiers. Cell-material-pillars are within the memory array region. The cell-material-pillars include channel material. The semiconductor material directly contacts the channel material. Conductive post structures are within the other region. Some of the conductive post structures are dummy structures and have bottom surfaces which are entirely along an insulative oxide material. Others of the conductive post structures are live posts electrically coupled with CMOS circuitry. Some embodiments include methods of forming assemblies.

公开(公告)号：US20240347464A1

公开(公告)日：2024-10-17

申请号：US18752525

申请日：2024-06-24

Applicant: Micron Technology, Inc.

Inventor： Lingyu Kong ,  Lifang Xu ,  Indra V. Chary ,  Shuangqiang Luo ,  Sok Han Wong

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/562 ,  H10B41/27 ,  H10B43/27

Abstract: A microelectronic device comprises a stack structure comprising insulative structures vertically interleaved with conductive structures, first support pillar structures vertically extending through the stack structure in a first staircase region including steps defined at edges of tiers of the insulative structures and conductive structures, and second support pillar structures vertically extending through the stack structure in a second staircase region including additional steps defined at edges of additional tiers of the insulative structures and conductive structures, the second support pillar structures having a smaller cross-sectional area than the first support pillar structures. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20240341095A1

公开(公告)日：2024-10-10

申请号：US18602321

申请日：2024-03-12

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Kar Wui Thong

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: Memory circuitry comprising strings of memory cells comprises vertically-alternating insulative tiers and conductive tiers that extend from a memory-array region into a stair-step region across an intermediate region that is between the memory-array region and the stair-step region. The insulative tiers and the conductive tiers comprise memory blocks upper portions of which individually comprise sub-blocks. Sub-block trenches are in the upper portions individually between immediately-laterally-adjacent of the sub-blocks. Strings of memory cells in the memory-array region comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks and in the sub-blocks. The sub-block trenches in the memory-array region, in the intermediate region, and in the stair-step region individually have a top. The top of individual of the sub-block trenches in the stair-step region has a narrowest-width that is larger than a narrowest-width of the top of the individual sub-block trenches in the intermediate region. The narrowest-width of the top of the individual sub-block trenches in the intermediate region is larger than a narrowest-width of the top of the individual sub-block trenches in the memory-array region. Other embodiments, including method, are disclosed.