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    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    51.
    发明公开
    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 审中-公开

    公开(公告)号：US20230320092A1

    公开(公告)日：2023-10-05

    申请号：US17713955

    申请日：2022-04-05

    Applicant: Micron Technology, Inc.

    Inventor： Collin Howder ,  John D. Hopkins

    IPC: H01L27/11582 ,  H01L27/11556

    CPC classification number: H01L27/11582 ,  H01L27/11556

    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above conductor material of a conductor tier. Channel-material-string constructions extend through the insulative and conductive tiers to a lowest of the conductive tiers. The channel-material-string constructions individually comprise a charge-blocking-material string, a storage-material string laterally-inward of the charge-blocking-material string, a charge-passage-material string laterally-inward of the storage-material string, and a channel-material string laterally-inward of the charge-passage-material string. Conductive material in the lowest conductive tier directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The conductive material is laterally-aside and laterally-inward of a laterally-inner sidewall of the charge-blocking-material string. Methods are disclosed.

    Integrated Assemblies, and Methods of Forming Integrated Assemblies
    54.
    发明申请
    Integrated Assemblies, and Methods of Forming Integrated Assemblies 有权

    公开(公告)号：US20220254810A1

    公开(公告)日：2022-08-11

    申请号：US17731103

    申请日：2022-04-27

    Applicant: Micron Technology, Inc.

    Inventor： Collin Howder ,  Gordon A. Haller

    IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11524

    Abstract: Some embodiments include an integrated structure having a stack of memory cell levels. A pair of channel-material-pillars extend through the stack. A source structure is under the stack. The source structure includes a portion having an upper region, a lower region, and an intermediate region between the upper and lower regions. The upper and lower regions have a same composition and join to one another at edge locations. The intermediate region has a different composition than the upper and lower regions. The edge locations are directly against the channel material of the channel-material-pillars. Some embodiments include methods of forming an integrated assembly.

    Integrated assemblies, and methods of forming integrated assemblies
    56.
    发明授权
    Integrated assemblies, and methods of forming integrated assemblies 有权

    公开(公告)号：US11348939B2

    公开(公告)日：2022-05-31

    申请号：US16723136

    申请日：2019-12-20

    Applicant: Micron Technology, Inc.

    Inventor： Collin Howder ,  Gordon A. Haller

    IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11524

    Abstract: Some embodiments include an integrated structure having a stack of memory cell levels. A pair of channel-material-pillars extend through the stack. A source structure is under the stack. The source structure includes a portion having an upper region, a lower region, and an intermediate region between the upper and lower regions. The upper and lower regions have a same composition and join to one another at edge locations. The intermediate region has a different composition than the upper and lower regions. The edge locations are directly against the channel material of the channel-material-pillars. Some embodiments include methods of forming an integrated assembly.

    Memory arrays and methods used in forming a memory array
    57.
    发明授权
    Memory arrays and methods used in forming a memory array 有权

    公开(公告)号：US11177269B2

    公开(公告)日：2021-11-16

    申请号：US16277311

    申请日：2019-02-15

    Applicant: Micron Technology, Inc.

    Inventor： Bharat Bhushan ,  Chris M. Carlson ,  Collin Howder

    IPC: H01L27/11556 ,  G11C8/14 ,  G11C16/04 ,  G06F3/06 ,  H01L27/11582 ,  H01L27/11529 ,  H01L27/11558 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11524

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. First charge-blocking material is formed to extend elevationally along the vertically-alternating tiers. The first charge-blocking material has k of at least 7.0 and comprises a metal oxide. A second charge-blocking material is formed laterally inward of the first charge-blocking material. The second charge-blocking material has k less than 7.0. Storage material is formed laterally inward of the second charge-blocking material. Insulative charge-passage material is formed laterally inward of the storage material. Channel material is formed to extend elevationally along the insulative tiers and the wordline tiers laterally inward of the insulative charge-passage material. Structure embodiments are disclosed.

    Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    59.
    发明申请
    Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 有权

    公开(公告)号：US20210167082A1

    公开(公告)日：2021-06-03

    申请号：US16702255

    申请日：2019-12-03

    Applicant: Micron Technology, Inc.

    Inventor： Collin Howder ,  Chet E. Carter

    IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

    Abstract: A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising an upper conductor material and a lower conductor material, and a stack comprising vertically-alternating first tiers and second tiers above the conductor tier. Horizontally-elongated trenches are formed through the stack to the upper conductor material and the lower conductor material. At least one of the upper and lower conductor materials have an exposed catalytic surface in the trenches. Metal material is electrolessly deposited onto the catalytic surface to cover the upper conductor material and the lower conductor material within the trenches. Channel-material strings of memory cells are formed and extend through the second tiers and the first tiers. Other embodiments, including structure independent of method, are disclosed.

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