公开(公告)号：US09825005B2

公开(公告)日：2017-11-21

申请号：US14960962

申请日：2015-12-07

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Yun-Hsin Yeh ,  Hung-Hsin Hsu

IPC: H01L25/04 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L21/683 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/10

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2924/1511 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/1815

Abstract: Disclosed is a semiconductor package with Pillar-Top-Interconnection (PTI) configuration, comprising a redistribution layer (RDL) formed on a carrier plane, a plurality of metal pillars disposed on the RDL, a chip bonded onto the RDL, and a molding core. The molding core is formed on the carrier plane and has a bottom surface defined by the carrier plane so that the RDL is embedded inside the molding core. The package thickness of the molding core is greater than the chip-bonding height of the chip so that the chip is completely embedded inside the molding core. The metal pillars are encapsulated at the peripheries of the molding core with a plurality of pillar top portions exposed from the molding core. The exposed pillar top portions are reentrant from a top surface of the molding core and uneven. Accordingly, it realizes the effects of ultra-thin and smaller footprint POP stacked assembly with fine pitch vertically electrical connections in POP structure. Also, it is possible to achieve zero spacing between POP stacked assembly.

公开(公告)号：US20170256471A1

公开(公告)日：2017-09-07

申请号：US15432932

申请日：2017-02-15

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Li-Chih Fang ,  Chia-Chang Chang ,  Hung-Hsin Hsu ,  Wen-Hsiung Chang ,  Kee-Wei Chung ,  Chia-Wen Lien

IPC: H01L23/31 ,  H01L23/00 ,  H01L27/146 ,  H01L21/56 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L23/3114 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/83 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14636 ,  H01L2224/0237 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/13016 ,  H01L2224/13027 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2924/0132 ,  H01L2924/15311

Abstract: A wafer level chip scale package (WLCSP) has a device chip, a carrier chip, an offset pad, a conductive spacing bump and a through hole via (THV). The device chip is attached to the carrier chip. The offset pad is disposed on a first surface of the device chip. The conductive spacing bump is formed on the offset pad. The through hole via includes a through hole and a hole metal layer. The through hole penetrates through the carrier chip and the device chip, and the hole metal layer is formed in the through hole and in contact with the offset pad.

公开(公告)号：US11990494B2

公开(公告)日：2024-05-21

申请号：US17383376

申请日：2021-07-22

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu

IPC: H01L27/146

CPC classification number: H01L27/14634 ,  H01L27/14618 ,  H01L27/1462 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/14689 ,  H01L27/1469

Abstract: A package structure including a first die, a second die, an encapsulant, a dam structure, a light-transmitting sheet, a conductive connector, a circuit layer, and a conductive terminal is provided. The first die includes a first active surface. The first active surface has a sensing area. The second die is arranged such that a second back surface thereof faces the first die. The encapsulant covers the second die. The encapsulant has a first encapsulating surface and a second encapsulating surface. The dam structure is located on the first encapsulating surface and exposes the sensing area. The light-transmitting sheet is located on the dam structure. The conductive connector penetrates the encapsulant. The circuit layer is located on the second encapsulating surface. The first die is electrically connected to the second die through the conductive connector and the circuit layer. The conductive terminal is disposed on the circuit layer.

公开(公告)号：US11916035B2

公开(公告)日：2024-02-27

申请号：US17392274

申请日：2021-08-03

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/73 ,  H01L24/19 ,  H01L24/20 ,  H01L24/26 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L23/481 ,  H01L24/16 ,  H01L24/24 ,  H01L24/32 ,  H01L2224/16145 ,  H01L2224/2101 ,  H01L2224/221 ,  H01L2224/24146 ,  H01L2224/26145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73217

Abstract: A packaging structure including first, second, and third dies, an encapsulant, a circuit structure, and a filler is provided. The encapsulant covers the first die. The circuit structure is disposed on the encapsulant. The second die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die has an optical signal transmission area. The filler is disposed between the second die and the circuit structure and between the third die and the circuit structure. A groove is present on an upper surface of the circuit structure. The upper surface includes first and second areas located on opposite sides of the groove. The filler directly contacts the first area. The filler is away from the second area. A manufacturing method of a packaging structure is also provided.

公开(公告)号：US11557533B2

公开(公告)日：2023-01-17

申请号：US17080853

申请日：2020-10-27

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18 ,  H01L21/56 ,  H01L21/683 ,  H01L25/065 ,  H01L25/16 ,  H01L25/00 ,  H01L23/31 ,  H01L23/538 ,  H01L23/24 ,  H01L21/78 ,  H01L23/16 ,  H01L23/367 ,  H01L23/552

Abstract: A package structure including a redistribution circuit structure, a first chip, a second chip, a first circuit board, a second circuit board, and a plurality of conductive terminals is provided. The redistribution circuit structure has a first connection surface and a second connection surface opposite to the first connection surface. The first chip and the second chip are disposed on the first connection surface and are electrically connected to the redistribution circuit structure. The first circuit board and the second circuit board are disposed on the second connection surface and are electrically connected to the redistribution circuit structure. The conductive terminals are disposed on the first circuit board or the second circuit board. The conductive terminals are electrically connected to the first circuit board or the second circuit board. A manufacturing method of a package structure is also provided.

公开(公告)号：US11456243B2

公开(公告)日：2022-09-27

申请号：US17080859

申请日：2020-10-27

Applicant: Powertech Technology Inc.

Inventor： Nan-Chun Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/18 ,  H01L21/56 ,  H01L21/683 ,  H01L25/065 ,  H01L25/16 ,  H01L25/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L23/24 ,  H01L21/78 ,  H01L23/16 ,  H01L23/367 ,  H01L23/552

Abstract: A semiconductor package structure, including a circuit substrate, at least two chips, an encapsulant, and a redistribution layer, is provided. The circuit substrate has a first surface and a second surface opposite to the first surface. The at least two chips are disposed on the first surface. Each of the at least two chips has an active surface facing the circuit substrate and includes multiple first conductive connectors and multiple second conductive connectors disposed on the active surface. A pitch of the first conductive connectors is less than a pitch of the second conductive connectors. The encapsulant encapsulates the at least two chips. The redistribution layer is located on the second surface. The first conductive connectors are electrically connected to the redistribution layer by the circuit substrate. The second conductive connectors are electrically connected to the circuit substrate. A manufacturing method of a semiconductor package structure is also provided.

公开(公告)号：US11257747B2

公开(公告)日：2022-02-22

申请号：US16382229

申请日：2019-04-12

Applicant: Powertech Technology Inc.

Inventor： Wen-Jeng Fan ,  Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/66

Abstract: A semiconductor package including a semiconductor chip, a conductive element disposed aside the semiconductor chip, a conductive via disposed on and electrically connected to the conductive element, an insulating encapsulation, and a first circuit structure disposed on the semiconductor chip and the conductive via is provided. A height of the conductive element is less than a height of the semiconductor chip. The insulating encapsulation encapsulates the semiconductor chip, the conductive element, and the conductive via. The conductive via is located between the first circuit structure and the conductive element, and the semiconductor chip is electrically coupled to the conductive via through the first circuit structure.

公开(公告)号：US11171106B2

公开(公告)日：2021-11-09

申请号：US16740496

申请日：2020-01-13

Applicant: Powertech Technology Inc.

Inventor： Nan-Chun Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package structure including a circuit substrate, at least one chip, an encapsulant, a plurality of conductive connectors, a redistribution layer, and a plurality of conductive terminals is provided. The circuit substrate has a first surface and a second surface opposite to the first surface. The at least one chip has an active surface and a rear surface opposite to the active surface. The at least one chip is disposed on the circuit substrate with the rear surface. The encapsulant encapsulates the at least one chip. The plurality of conductive connectors surrounds the at least one chip. The redistribution layer is located on the encapsulant. The plurality of conductive terminals is located on the second surface. The at least one chip is electrically connected to the plurality of conductive terminals via the redistribution layer, the plurality of conductive connectors, and the circuit substrate. A manufacturing method of a semiconductor package structure is also provided.

公开(公告)号：US11088080B2

公开(公告)日：2021-08-10

申请号：US16679326

申请日：2019-11-11

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Pei-Chun Tsai ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien ,  Nan-Chun Lin

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

Abstract: A chip package structure using silicon interposer as interconnection bridge lifts multi-dies above the fan-out molding package embedded with premade Si interposer interconnection bridge under the multi-die space. The interconnection bridge connects the multi-dies through fine pitch high I/O interconnection. A first RDL and a second RDL are further disposed on top side and bottom side of the fan-out molding package, further providing connection for the multi-dies to a substrate via the connection routing inside the fan-out molding package.

公开(公告)号：US20210202459A1

公开(公告)日：2021-07-01

申请号：US17099802

申请日：2020-11-17

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L25/18 ,  H01L25/065 ,  H01L25/16 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00

Abstract: A package structure including a first chip, a second chip, a dielectric body, a third chip, an encapsulant, a first conductive terminal, and a circuit layer is provided. The dielectric body covers the first chip and the second chip. The third chip is disposed on the dielectric body such that a third active surface thereof faces a first active surface of the first chip or a second active surface of the second chip. The encapsulant covers the third chip. The first conductive terminal is disposed on the dielectric body and is opposite to the third chip. The circuit layer includes a first circuit portion and a second circuit portion. The first circuit portion penetrates the dielectric body. The first chip, the second chip, or the third chip is electrically connected to the first conductive terminal through the first circuit portion. The second circuit portion is embedded in the dielectric body.