公开(公告)号：US20220004472A9

公开(公告)日：2022-01-06

申请号：US16670798

申请日：2019-10-31

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent S. Haukness ,  John Eric Linstadt ,  Scott C. Best

IPC: G06F11/20 ,  G11C29/52 ,  G11C11/4093

Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

公开(公告)号：US11108510B2

公开(公告)日：2021-08-31

申请号：US16861164

申请日：2020-04-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Richard E. Perego ,  Craig E. Hampel

IPC: H04L7/00 ,  H04L1/24 ,  H04L7/10 ,  H04L25/02 ,  H04L25/12 ,  G11C29/02 ,  G11C7/10 ,  H04L27/00 ,  G11C7/04 ,  H04L7/033

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

公开(公告)号：US11075671B2

公开(公告)日：2021-07-27

申请号：US16685861

申请日：2019-11-15

Applicant: Rambus Inc.

Inventor： John W. Poulton ,  Frederick A. Ware ,  Carl W. Werner

IPC: H04B3/56 ,  H04L25/02 ,  G06F13/40 ,  H03F3/24 ,  H04B3/54 ,  H04B10/50 ,  H04B10/40 ,  H04B10/073 ,  H04B1/04

Abstract: A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.

公开(公告)号：US20210183434A1

公开(公告)日：2021-06-17

申请号：US17115538

申请日：2020-12-08

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness

IPC: G11C11/406 ,  G06F13/16

Abstract: The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.

公开(公告)号：US11029715B1

公开(公告)日：2021-06-08

申请号：US16853644

申请日：2020-04-20

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: G05F1/567 ,  G05F1/56

Abstract: A voltage converter includes first and second inputs to receive a supply voltage and a reference voltage, respectively, from a power supply component, the supply voltage being higher than the reference voltage by a scaling factor of at least five. The voltage converter iteratively charges an internal filter capacitor to produce a converted voltage that follows the reference voltage by switchably coupling the first input to the filter capacitor while the converted voltage is less than the reference voltage to raise the converted voltage, and by switchably decoupling the first input from the filter capacitor while the converted voltage exceeds the reference voltage to enable the converted voltage to decay.

公开(公告)号：US20210098033A1

公开(公告)日：2021-04-01

申请号：US17065278

申请日：2020-10-07

Applicant: Rambus Inc.

Inventor： James E. Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC: G11C7/10 ,  G11C7/08 ,  G11C5/02 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

公开(公告)号：US20210089464A1

公开(公告)日：2021-03-25

申请号：US17064342

申请日：2020-10-06

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F12/0895 ,  G06F12/0846 ,  G11C8/06 ,  G06F12/1027 ,  G06F12/0802

Abstract: A memory controller includes logic circuitry to generate a first data address identifying a location in a first external memory array for storing first data, a first tag address identifying a location in a second external memory array for storing a first tag, a second data address identifying a location in the second external memory array for storing second data, and a second tag address identifying a location in the first external memory array for storing a second tag. The memory controller includes an interface that transfers the first data address and the first tag address for a first set of memory operations in the first and the second external memory arrays. The interface transfers the second data address and the second tag address for a second set of memory operations in the first and the second external memory arrays.

公开(公告)号：US20210044417A1

公开(公告)日：2021-02-11

申请号：US17000182

申请日：2020-08-21

Applicant: Rambus Inc.

Inventor： Bret G. Stott ,  Craig E. Hampel ,  Frederick A. Ware

IPC: H04L7/033 ,  H04L7/00 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  H03L7/081 ,  H04L1/20

Abstract: A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.

公开(公告)号：US20210027825A1

公开(公告)日：2021-01-28

申请号：US16896056

申请日：2020-06-08

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Richard E. Perego ,  Craig E. Hampel

IPC: G11C11/4076 ,  G11C7/10 ,  G06F13/16 ,  G06F13/40 ,  G11C5/06 ,  G11C29/02 ,  G11C29/50 ,  G11C8/18 ,  G11C7/22 ,  G06F1/10 ,  G11C11/409 ,  G11C11/4096 ,  G06F1/06 ,  G06F1/12 ,  G06F3/06

Abstract: A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.

公开(公告)号：US10819447B2

公开(公告)日：2020-10-27

申请号：US16692029

申请日：2019-11-22

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Frederick A. Ware ,  Richard E. Perego

IPC: H04L7/00 ,  H04B17/00 ,  H04B17/11 ,  H04L7/04 ,  H04L7/10 ,  H04L27/00 ,  H04B17/21

Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.