公开(公告)号：US20240260274A1

公开(公告)日：2024-08-01

申请号：US18414933

申请日：2024-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dukhyun CHOE ,  Jinseong HEO ,  Hyunjae LEE ,  Seunggeol NAM ,  Yoonsang PARK ,  Sijung YOO

IPC: H10B51/20 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H10B53/20

CPC classification number: H10B51/20 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/78391 ,  H10B53/20

Abstract: Provided are a memory device implementing multi-bit functionality and a memory apparatus including the memory device. The memory device includes a semiconductor substrate, a gate electrode on the semiconductor substrate, and a plurality of ferroelectric layers laminated between the semiconductor substrate and the gate electrode in a first direction perpendicular to a surface of the semiconductor substrate and including at least one first ferroelectric layer and at least one second ferroelectric layer. The first ferroelectric layer has a doping concentration gradient in which a doping concentration increases in the first direction, and the second ferroelectric layer has a doping concentration gradient in which a doping concentration decreases in the first direction. The memory device is configured to implement multi-bit functionality according to an operating voltage.

公开(公告)号：US20240172448A1

公开(公告)日：2024-05-23

申请号：US18492130

申请日：2023-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol NAM ,  Jinseong HEO ,  Hyunjae LEE ,  Dukhyun CHOE

IPC: H10B51/20 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H10B51/10

CPC classification number: H10B51/20 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/10

Abstract: A three-dimensional (3D) ferroelectric memory device may include a substrate; a plurality of insulating layers stacked on the substrate; a plurality of gate electrodes between the plurality of insulating layers; a plurality of ferroelectric layers in contact with the plurality of gate electrodes; a plurality of intermediate electrodes in contact with the plurality of ferroelectric layers and protruding from side surfaces of the plurality of insulating layers; a gate insulating layer in contact with the plurality of intermediate electrodes and the plurality of insulating layers; and a channel layer in contact with the gate insulating layer.

公开(公告)号：US20240006509A1

公开(公告)日：2024-01-04

申请号：US18468394

申请日：2023-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Taehwan MOON ,  Seunggeol NAM ,  Sanghyun JO

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B53/30

CPC classification number: H01L29/516 ,  H01L29/78391 ,  H01L29/40111 ,  H01L28/60 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/6684 ,  H01L29/7851 ,  H01L29/78696 ,  H10B53/30

Abstract: A thin film structure including ferroelectrics and anti-ferroelectrics and a semiconductor device including the same are provided. The thin film structure includes a first anti-ferroelectric layer comprising anti-ferroelectrics, a second anti-ferroelectric layer disposed apart from the first anti-ferroelectric layer and including anti-ferroelectrics, and a ferroelectric layer between the first anti-ferroelectric layer and the second anti-ferroelectric layer and including ferroelectrics.

公开(公告)号：US20230121102A1

公开(公告)日：2023-04-20

申请号：US17964365

申请日：2022-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehwan MOON ,  Jinseong HEO ,  Seunggeol NAM ,  Dukhyun CHOE

IPC: H01L29/92 ,  H01L29/43

Abstract: A capacitor device and a semiconductor device including the capacitor device are provided. The capacitor device includes first and second electrodes spaced apart from each other, and a dielectric layer provided between the first electrode and the second electrode. The dielectric layer includes a dielectric material in which ferroelectrics and antiferroelectrics are mixed with each other.

公开(公告)号：US20230099577A1

公开(公告)日：2023-03-30

申请号：US17953491

申请日：2022-09-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Hagyoul BAE ,  Seunggeol NAM ,  Hyunjae LEE ,  Dukhyun CHOE

IPC: G11C15/04

Abstract: Provided is a content-addressable memory. The content-addressable memory may include a memory cell connected to a match line, a word line, and a search line, and the memory cell includes a first channel layer and a second channel layer doped with different dopants.

公开(公告)号：US20230062878A1

公开(公告)日：2023-03-02

申请号：US17894504

申请日：2022-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Yunseong LEE ,  Hyangsook LEE ,  Sanghyun JO ,  Seunggeol NAM ,  Taehwan MOON ,  Hagyoul BAE ,  Eunha LEE ,  Junho LEE

IPC: H01L29/78 ,  H01L29/51

Abstract: An electronic device includes: a substrate including a source, a drain, and a channel between the source and the drain; a gate electrode arranged above the substrate and facing the channel, the gate electrode being apart from the channel in a first direction; and a ferroelectric thin film structure between the channel and the gate electrode, the ferroelectric thin film structure including a first ferroelectric layer, a crystallization barrier layer including a dielectric material, and a second ferroelectric layer, which are sequentially arranged from the channel in the first direction. The average of sizes of crystal grains of the first ferroelectric layer may be less than or equal to the average of sizes of crystal grains of the second ferroelectric layer, and owing to small crystal grains, dispersion of performance may be improved.

公开(公告)号：US20220351776A1

公开(公告)日：2022-11-03

申请号：US17540675

申请日：2021-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol NAM ,  Jinseong HEO ,  Taehwan MOON ,  Hagyoul BAE

IPC: G11C15/04

Abstract: Disclosed are a non-volatile content addressable memory device having a simple cell configuration and/or an operating method thereof. The non-volatile content addressable memory device includes a plurality of unit cells, wherein each of the plurality of unit cells consists of or includes a first ferroelectric transistor and a second ferroelectric transistor The first and second ferroelectric transistors are of different types such as different electrical types from each other. The first and second ferroelectric transistors may be connected in series or in parallel to each other. The first and second ferroelectric transistors may share one word line and one match line. The first and second ferroelectric transistors may share one search line. One of the first and second ferroelectric transistors may be connected to a search line and the other one may be connected to a bar search line. The first and second ferroelectric transistors may share one match line.

公开(公告)号：US20210123161A1

公开(公告)日：2021-04-29

申请号：US17082502

申请日：2020-10-28

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Changseok LEE ,  Hyeonsuk SHIN ,  Hyeonjin SHIN ,  Seokmo HONG ,  Minhyun LEE ,  Seunggeol NAM ,  Kyungyeol MA

IPC: C30B29/38 ,  H01L21/02

Abstract: A boron nitride layer and a method of fabricating the same are provided. The boron nitride layer includes a boron nitride compound and has a dielectric constant of about 2.5 or less at an operating frequency of 100 kHz.

公开(公告)号：US20210074815A1

公开(公告)日：2021-03-11

申请号：US17087968

申请日：2020-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Hyeonjin SHIN ,  Yeonchoo CHO ,  Seunggeol NAM ,  Seongjun PARK ,  Yunseong LEE

IPC: H01L29/16 ,  H01L21/02 ,  C01B32/186

Abstract: Provided is a semiconductor device including graphene. The semiconductor device includes: a substrate including an insulator and a semiconductor; and a graphene layer configured to directly grow only on a surface of the semiconductor, wherein the semiconductor includes at least one of a group IV material and a group III-V compound.

公开(公告)号：US20200286732A1

公开(公告)日：2020-09-10

申请号：US16807702

申请日：2020-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Janghee LEE ,  Seunggeol NAM ,  Hyeonjin SHIN ,  Hyunseok LIM ,  Alum JUNG ,  Kyung-Eun BYUN ,  Jeonil LEE ,  Yeonchoo CHO

IPC: H01L21/02 ,  C23C16/02 ,  C23C16/26

Abstract: Provided are a method of pre-treating a substrate and a method of directly forming graphene by using the method of pre-treating the substrate. In the method of pre-treating the substrate in the method of directly forming graphene, according to an embodiment, the substrate is pre-treated by using a pre-treatment gas including at least a carbon source and hydrogen. The method of directly forming graphene includes a process of pre-treating a substrate and a process of directly growing graphene on the substrate that is pre-treated. The process of pre-treating the substrate is performed according to the method of pre-treating the substrate.