Semiconductor memory devices and methods of operating semiconductor memory devices

    公开(公告)号:US11487615B2

    公开(公告)日:2022-11-01

    申请号:US17205276

    申请日:2021-03-18

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a scrubbing control circuit and a control logic circuit. The memory cell array includes memory cell rows, and each of the memory cell rows including volatile memory cells. The scrubbing control circuit generates scrubbing addresses for performing a normal scrubbing operation on the memory cell rows with a first period based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC engine the scrubbing control circuit to distribute a scrubbing operation on weak codewords dynamically within the refresh operation such that a dynamic allocated scrubbing (DAS) operation is performed with a second period smaller than the first period. An error bit is detected in each of the weak codewords during the normal scrubbing operation or normal read operation on at least one of the memory cell rows.

    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES

    公开(公告)号:US20220093200A1

    公开(公告)日:2022-03-24

    申请号:US17245075

    申请日:2021-04-30

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register, a scrubbing control circuit and a control logic circuit. The memory cell array includes memory cell rows. The scrubbing control circuit generates scrubbing addresses based on refresh operations performed on the memory cell array. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection operation on a plurality of sub-pages in a first memory cell row to count a number of error occurrences, and determines whether to correct a codeword in which an error is detected based on the number of error occurrences. An uncorrected or corrected codeword is written back , and a row address of the first memory cell row may be stored in the fault address register as a row fault address based on the number of error occurrences.

    Conductive structure disposed to correspond to antenna module and electronic device including the same

    公开(公告)号:US10819018B2

    公开(公告)日:2020-10-27

    申请号:US16573290

    申请日:2019-09-17

    Abstract: An electronic device is provided. The electronic device includes a housing including a first plate facing in a first direction, a second plate opposite to the first plate and facing in a second direction, and a side member enclosing a space between the first plate and the second plate, an antenna structure including at least one antenna element disposed substantially parallel to the second plate in the space and disposed to face the second plate, a conductive structure disposed in the space and including an opening, the antenna structure being disposed to at least partially overlap the opening when viewed from above the second plate, and a wireless communication circuit configured to form a directional beam through the at least one antenna element. In addition, various embodiments may be available.

    Electronic device supporting beamforming and method of operating electronic device

    公开(公告)号:US10568039B2

    公开(公告)日:2020-02-18

    申请号:US15903320

    申请日:2018-02-23

    Abstract: An electronic device supporting beamforming and a method of operating the electronic device are provided. The electronic device includes a first amplifier configured to amplify a first signal and a second amplifier for amplifying a second signal, a power control module configured to generate first power control information based at least on a first attribute of the first signal and generate second power control information based at least on the first power control information and a second attribute of the second signal, and at least one power supply module configured to control power supplied to the first amplifier based at least on the first power control information and control power supplied to the second amplifier based at least on the second power control information.

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