公开(公告)号：US20110044121A1

公开(公告)日：2011-02-24

申请号：US12860484

申请日：2010-08-20

Applicant: Joung-Yeal Kim ,  Soo-Bong Chang ,  Seong-Jin Jang ,  Jin-Seok Kwak ,  Dong-Hak Shin

Inventor： Joung-Yeal Kim ,  Soo-Bong Chang ,  Seong-Jin Jang ,  Jin-Seok Kwak ,  Dong-Hak Shin

IPC: G11C7/06

CPC classification number: G11C11/4094 ,  G11C11/4091 ,  G11C2207/005

Abstract: A semiconductor memory device includes a memory cell array block including a plurality of memory cells each connected to one of a plurality of bit lines and one of a plurality of word lines, a sense amplifier connected to a half of the plurality of bit lines, the sense amplifier for sensing and amplifying a voltage between each of the half of the bit lines and a corresponding complementary bit line; and a dummy block connected to the half of the plurality of bit lines of the memory cell array block, the dummy block for controlling a load on the memory cell array block to be different from a load on the dummy block according to a dummy load signal.

Abstract translation: 半导体存储器件包括存储单元阵列块，该存储单元阵列块包括多个存储单元，每个存储单元分别连接到多个位线中的一个位线和多个字线中的一个，连接到多个位线的一半的读出放大器， 读出放大器，用于感测和放大位线的每一个之间的电压和相应的互补位线; 以及连接到存储单元阵列块的多个位线的一半的虚拟块，用于根据虚拟负载信号控制存储单元阵列块上的负载与虚拟块上的负载不同的虚拟块 。

公开(公告)号：US07830280B2

公开(公告)日：2010-11-09

申请号：US12453109

申请日：2009-04-29

Applicant: Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

Inventor： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

IPC: H03M5/00

CPC classification number: H03K19/00346 ,  H04L25/03866 ,  H04L25/14 ,  H04L25/4908

Abstract: Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

Abstract translation: 提供半导体器件，包括所述半导体器件的系统及其方法。 半导体器件的示例可以接收被调度用于传输的数据，对接收到的数据内的比特数进行加扰，根据给定的伪随机序列排列的加扰顺序。 所接收的数据可以是平衡的，使得等于第一逻辑电平的接收数据内的第一比特数与等于第二逻辑电平的接收数据中的第二比特数之间的差异低于阈值。 然后可以发送平衡和加扰的接收数据。 示例半导体器件可以以任何顺序执行加扰和平衡操作。 类似地，在接收端，另一个半导体器件可以通过对发送的数据进行解扰和不平衡来解码原始数据。 可以基于发送的数据被加扰和平衡的顺序以顺序执行解扰和不平衡操作。

公开(公告)号：US20100259426A1

公开(公告)日：2010-10-14

申请号：US12824156

申请日：2010-06-26

Applicant: Seung-Jun Bae ,  Seong-Jin Jang

Inventor： Seung-Jun Bae ,  Seong-Jin Jang

IPC: H03M5/00

CPC classification number: H03M5/145

Abstract: DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data.

Abstract translation: 通过发送伪数据的前导码来发送DC平衡编码数据，该伪数据的前导码被配置为提供给定逻辑值的中间位数，该给定逻辑值是给定逻辑值的至少一位，但小于给定逻辑值的最大位数 DC平衡编码数据中的逻辑值，从而减少由DC平衡编码数据的第一字的传输引起的同时开关噪声。 前导码可以包含固定和/或可变虚拟数据的一个或多个单词。

公开(公告)号：US20100226192A1

公开(公告)日：2010-09-09

申请号：US12659328

申请日：2010-03-04

Applicant: Jong-Ho Moon ,  Seong-Jin Jang

Inventor： Jong-Ho Moon ,  Seong-Jin Jang

IPC: G11C7/00

CPC classification number: G11C7/1048 ,  G11C11/4096

Abstract: A data path circuit of a semiconductor memory device includes: a bit line sense amplifier driven by a first power supply voltage; a local input/output line sense amplifier; a column selecting unit operatively connecting a pair of bit lines connected to the bit line sense amplifier and a pair of local input/output lines connected to the local input/output line sense amplifier in response to a column selection signal; and a local input/output line precharge unit precharging the pair of local input/output lines with a second power supply voltage different from the first power supply voltage during a period for which the column selection signal is in an inactive state.

Abstract translation: 半导体存储器件的数据路径电路包括：由第一电源电压驱动的位线读出放大器; 本地输入/输出线路读出放大器; 列选择单元，可操作地连接连接到位线读出放大器的一对位线和响应于列选择信号连接到本地输入/输出线读出放大器的一对本地输入/输出线; 以及本地输入/输出线预充电单元，在列选择信号处于非活动状态的期间，用与第一电源电压不同的第二电源电压对一对本地输入/输出线进行预充电。

公开(公告)号：US07733715B2

公开(公告)日：2010-06-08

申请号：US12071347

申请日：2008-02-20

Applicant: Kwang-Il Park ,  Seong-Jin Jang ,  Ho-Young Song

Inventor： Kwang-Il Park ,  Seong-Jin Jang ,  Ho-Young Song

IPC: G11C7/00

CPC classification number: G11C7/1051 ,  G11C7/1066 ,  G11C2207/2254

Abstract: An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory devices, wherein the memory controller provides a command signal and a chip selecting signal to the semiconductor memory devices. One or more of the semiconductor memory devices may detect a read command and a dummy read command in response to the command signal and the chip selecting signal and generate one or more preamble signals based on a calculated preamble cycle number.

Abstract translation: 输出数据选通信号产生方法和包括多个半导体存储器件的存储器系统以及用于控制半导体存储器件的存储器控​​制器，其中存储器控制器向半导体存储器件提供命令信号和片选信号。 一个或多个半导体存储器件可以响应于命令信号和芯片选择信号来检测读取命令和伪读取命令，并且基于所计算的前导码周期数生成一个或多个前导码信号。

公开(公告)号：US20100091601A1

公开(公告)日：2010-04-15

申请号：US12635751

申请日：2009-12-11

Applicant: Seung-Jun Bae ,  Kwang-Il Park ,  Seong-Jin Jang

Inventor： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-Jin Jang

IPC: G11C8/00

CPC classification number: G11C7/22 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222

Abstract: A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller includes an edge information storage unit which stores edge information output from the semiconductor memory device, a pseudo data pattern generating unit which outputs pseudo data including a pattern similar to actually transmitted data, a phase detecting unit which receives the edge information from the edge information storage unit and the pseudo data from the pseudo data pattern generating unit to detect a phase difference between the data and the clock signal and generate a corresponding detection result, and a phase control unit which controls a phase of the clock signal according to the corresponding detection result from the phase detecting unit, so as to eliminate a per-data input/output pin skew in a data write and read operation of the semiconductor memory device.

Abstract translation: 一种用于消除半导体存储器件和存储器控制器之间的接口中的数据与时钟信号之间的偏斜的电路，包括存储从半导体存储器件输出的边沿信息的边缘信息存储单元，伪数据模式生成单元，其输出伪 数据，包括与实际发送的数据类似的模式;相位检测单元，其从边缘信息存储单元接收边缘信息，并从伪数据模式产生单元接收伪数据，以检测数据和时钟信号之间的相位差，并产生 相应的检测结果，以及相位控制单元，其根据来自相位检测单元的相应检测结果控制时钟信号的相位，以便消除数据写入和读取操作中的每数据输入/输出引脚偏移 的半导体存储器件。

公开(公告)号：US07499341B2

公开(公告)日：2009-03-03

申请号：US11601027

申请日：2006-11-17

Applicant: Woo-Jin Lee ,  Hyun-Dong Kim ,  Seong-Jin Jang

Inventor： Woo-Jin Lee ,  Hyun-Dong Kim ,  Seong-Jin Jang

IPC: G11C7/10

CPC classification number: G11C29/48 ,  G11C7/1051 ,  G11C7/1069 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/14

Abstract: A semiconductor memory device and a method of expanding a valid output data window are described. The semiconductor memory device includes a memory cell array and an output circuit. The memory cell array generates read data having a plurality of bits. The output circuit outputs the read data sequentially in response to a clock signal in a normal mode. On the other hand, the output circuit selectively outputs the bits of the read data by latching bits to be tested among bits of the read data, and by electrically disconnecting bits not to be tested among bits of the read data in response to a plurality of switch control signals in a test mode. Therefore a valid data window of an output data may be expanded.

Abstract translation: 描述半导体存储器件和扩展有效输出数据窗口的方法。 半导体存储器件包括存储单元阵列和输出电路。 存储单元阵列产生具有多个位的读取数据。 输出电路响应于正常模式下的时钟信号顺序地输出读取的数据。 另一方面，输出电路通过在读取数据的比特之间锁存待测试的比特来选择性地输出读取的数据的比特，并且响应于多个读取数据，通过电连接在读取的数据的比特之间的不被测试的比特 在测试模式下切换控制信号。 因此，可以扩展输出数据的有效数据窗口。

公开(公告)号：US20080291753A1

公开(公告)日：2008-11-27

申请号：US12219816

申请日：2008-07-29

Applicant: Kwang-Il Park ,  Young-Hyun Jun ,  Seong-Jin Jang ,  Ho-Young Song

Inventor： Kwang-Il Park ,  Young-Hyun Jun ,  Seong-Jin Jang ,  Ho-Young Song

IPC: G11C7/00 ,  G11C8/18

CPC classification number: G11C7/1051 ,  G11C7/1066 ,  G11C7/1072

Abstract: A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal.

Abstract translation: 公开了等待信号产生方法和相应的半导体存储器件。 这种方法包括：接收半导体存储器件的时钟信号; 接收模式表征信号; 提供DQS; 以及根据模式表征信号调整DQS的前导码状态的持续时间，以促进DQS的选通状态与时钟信号的一致性。

公开(公告)号：US07453745B2

公开(公告)日：2008-11-18

申请号：US11416077

申请日：2006-05-03

Applicant: Kwang-Il Park ,  Young-Hyun Jun ,  Seong-Jin Jang ,  Ho-Young Song

Inventor： Kwang-Il Park ,  Young-Hyun Jun ,  Seong-Jin Jang ,  Ho-Young Song

IPC: G11C7/00

CPC classification number: G11C7/1051 ,  G11C7/1066 ,  G11C7/1072

Abstract: A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal.

公开(公告)号：US07420387B2

公开(公告)日：2008-09-02

申请号：US11402123

申请日：2006-04-11

Applicant: Woo-Jin Lee ,  Kwang-Il Park ,  Hyun-Jin Kim ,  Seong-Jin Jang

Inventor： Woo-Jin Lee ,  Kwang-Il Park ,  Hyun-Jin Kim ,  Seong-Jin Jang

IPC: H03K17/16

CPC classification number: H03K19/0005

Abstract: Provided is a semiconductor device capable of controlling an on-die-termination (ODT) circuit and an off-chip-driver (OCD) circuit and a control method used by the semiconductor device. The semiconductor device includes a control code generation unit generating a control code in response to a control signal, an addition unit adding an adjustment code to the control code to produce an adjusted control code, and an ODT circuit, wherein an impedance of the ODT circuit is adjusted in response to the adjusted control code. The semiconductor device can adjust the control code more precisely by adding or subtracting the adjustment code to or from the control code. Accordingly, the impedance of an OCD circuit or ODT circuit can be adjusted more precisely.

Abstract translation: 提供了能够控制芯片上终端（ODT）电路和芯片外驱动器（OCD）电路的半导体器件以及由半导体器件使用的控制方法。 半导体器件包括响应于控制信号产生控制代码的控制代码生成单元，向控制代码添加调整代码以产生调整后的控制代码的加法单元和ODT电路，其中ODT电路的阻抗 根据调整后的控制代码进行调整。 半导体器件可以通过向或从控制代码添加或减去调整代码来更精确地调整控制代码。 因此，可以更精确地调整OCD电路或ODT电路的阻抗。