中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

77 records (took 0.019 seconds)

    SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF
    51.
    发明申请
    SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF 审中-公开
    半导体封装及其制造方法

    公开(公告)号：US20150179597A1

    公开(公告)日：2015-06-25

    申请号：US14183872

    申请日：2014-02-19

    Applicant: Siliconware Precision Industries Co., Ltd

    Inventor： Pai-Yuan Li ,  Chun-Tang Lin

    IPC: H01L23/00 ,  H01L23/29

    CPC classification number: H01L24/17 ,  C08K2201/005 ,  C09J9/02 ,  H01L21/563 ,  H01L23/295 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/2939 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/83104 ,  H01L2224/83862 ,  H01L2224/83909 ,  H01L2224/92125 ,  H01L2924/01082 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012

    Abstract: A semiconductor package is provided, which includes: a first electronic element; a plurality of conductive elements formed on the first electronic element; a second electronic element having a plurality of conductive bumps and disposed on the first electronic element through the conductive bumps, wherein the conductive bumps are correspondingly electrically connected to the conductive elements; and an underfill formed between the second electronic element and the first electronic element for encapsulating the conductive bumps and the conductive elements, wherein the underfill contains a plurality of conductive particles having a particle size between 0.1 and 1 um, a plurality of insulating particles having a particle size between 1 and 10 um and a polymer. The invention overcomes the conventional drawback of poor electrical connection between the second electronic element and the first electronic element through the conductive particles so as to enhance the electrical performance of the semiconductor package.

    Abstract translation: 提供一种半导体封装，其包括：第一电子元件; 形成在所述第一电子元件上的多个导电元件; 具有多个导电凸块的第二电子元件，并且通过导电凸块设置在第一电子元件上，其中导电凸块相应地电连接到导电元件; 以及在所述第二电子元件和所述第一电子元件之间形成的用于封装所述导电凸块和所述导电元件的底部填充物，其中所述底部填充物包含多个粒径为0.1μm至1μm的导电颗粒，所述多个绝缘颗粒具有 颗粒尺寸在1到10μm之间，聚合物。 本发明克服了通过导电颗粒导致第二电子元件与第一电子元件之间的不良电连接的传统缺点，从而提高半导体封装的电性能。

    SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
    55.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME 审中-公开
    半导体封装及其制造方法

    公开(公告)号：US20150014864A1

    公开(公告)日：2015-01-15

    申请号：US14074208

    申请日：2013-11-07

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Wan-Ting Chen ,  Chun-Tang Lin ,  Yi-Che Lai

    IPC: H01L23/28 ,  H01L21/56

    CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/16 ,  H01L2224/16235 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00

    Abstract: The present invention provides a semiconductor package and a method of fabricating the same. The semiconductor package includes a substrate, a package unit mounted on and electrically connected to the substrate, and a second encapsulant formed on the substrate and encapsulating the package unit. The package unit includes an interposer, a semiconductor chip mounted on the interposer in a flip-chip manner, and a first encapsulant formed on the interposer and encapsulating the semiconductor chip. The present invention reduces the fabricating time and increases the yield of the final product.

    Abstract translation: 本发明提供一种半导体封装及其制造方法。 半导体封装包括衬底，安装在衬底上并电连接到衬底的封装单元，以及形成在衬底上并封装封装单元的第二密封剂。 封装单元包括插入器，以倒装芯片方式安装在插入器上的半导体芯片，以及形成在插入器上并封装半导体芯片的第一密封剂。 本发明减少了制造时间并提高了最终产品的产率。

    Semiconductor package and fabrication method thereof
    56.
    发明授权
    Semiconductor package and fabrication method thereof 有权
    半导体封装及其制造方法

    公开(公告)号：US08829687B2

    公开(公告)日：2014-09-09

    申请号：US13722138

    申请日：2012-12-20

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Mu-Hsuan Chan ,  Wan-Ting Chen ,  Yi-Chian Liao ,  Chun-Tang Lin ,  Yi-Chi Lai

    IPC: H01L23/48 ,  H01L21/00 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498

    CPC classification number: H01L23/49811 ,  H01L21/486 ,  H01L21/78 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00

    Abstract: A semiconductor package is provided, which includes: a semiconductor substrate having opposite first and second surfaces; an adhesive layer formed on the first surface of the semiconductor substrate; at least a semiconductor chip disposed on the adhesive layer; an encapsulant formed on the adhesive layer for encapsulating the semiconductor chip; and a plurality of conductive posts penetrating the first and second surfaces of the semiconductor substrate and the adhesive layer and electrically connected to the semiconductor chip, thereby effectively reducing the fabrication cost, shortening the fabrication time and improving the product reliability.

    Abstract translation: 提供一种半导体封装，其包括：具有相反的第一和第二表面的半导体衬底; 形成在所述半导体衬底的第一表面上的粘合剂层; 至少设置在所述粘合剂层上的半导体芯片; 形成在用于封装半导体芯片的粘合剂层上的密封剂; 以及贯穿半导体衬底的第一和第二表面和粘合剂层并且电连接到半导体芯片的多个导电柱，从而有效地降低了制造成本，缩短了制造时间并提高了产品的可靠性。

    SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF
    57.
    发明申请
    SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF 有权
    半导体封装及其制造方法

    公开(公告)号：US20140084484A1

    公开(公告)日：2014-03-27

    申请号：US13922828

    申请日：2013-06-20

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Mu-Hsuan Chan ,  Wan-Ting Chen ,  Chun-Tang Lin ,  Yi-Che Lai

    IPC: H01L23/00

    CPC classification number: H01L23/562 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2924/351 ,  H01L2924/00

    Abstract: A semiconductor package is provided, which includes: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top surface of the interposer; a redistribution layer formed on the encapsulant and the top surface of the interposer; and at least a semiconductor element disposed on the redistribution layer. The top surface of the interposer is flush with a surface of the encapsulant so as for the redistribution layer to have a planar surface for disposing the semiconductor element, thereby preventing warpage of the interposer and improving the reliability of electrical connection between the redistribution layer and the semiconductor element.

    Abstract translation: 提供一种半导体封装，其包括：载体; 至少设置在所述载体上的插入件; 形成在所述载体上的密封剂，用于在暴露所述插入件的顶表面的同时封装所述插入件; 在所述密封剂和所述插入件的顶表面上形成的再分布层; 以及设置在再分布层上的至少一个半导体元件。 插入器的顶表面与密封剂的表面齐平，以使再分布层具有用于设置半导体元件的平坦表面，从而防止插入件的翘曲，并提高再分布层与第二层之间的电连接的可靠性 半导体元件。

    SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF
    58.
    发明申请
    SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF 有权
    半导体封装及其制造方法

    公开(公告)号：US20140084455A1

    公开(公告)日：2014-03-27

    申请号：US13722138

    申请日：2012-12-20

    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

    Inventor： Mu-Hsuan Chan ,  Wan-Ting Chen ,  Yi-Chian Liao ,  Chun-Tang Lin ,  Yi-Chi Lai

    IPC: H01L23/498 ,  H01L21/78

    CPC classification number: H01L23/49811 ,  H01L21/486 ,  H01L21/78 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00

    Abstract: A semiconductor package is provided, which includes: a semiconductor substrate having opposite first and second surfaces; an adhesive layer formed on the first surface of the semiconductor substrate; at least a semiconductor chip disposed on the adhesive layer; an encapsulant formed on the adhesive layer for encapsulating the semiconductor chip; and a plurality of conductive posts penetrating the first and second surfaces of the semiconductor substrate and the adhesive layer and electrically connected to the semiconductor chip, thereby effectively reducing the fabrication cost, shortening the fabrication time and improving the product reliability.

    Abstract translation: 提供一种半导体封装，其包括：具有相反的第一和第二表面的半导体衬底; 形成在所述半导体衬底的第一表面上的粘合剂层; 至少设置在所述粘合剂层上的半导体芯片; 形成在用于封装半导体芯片的粘合剂层上的密封剂; 以及贯穿半导体衬底的第一和第二表面和粘合剂层并且电连接到半导体芯片的多个导电柱，从而有效地降低了制造成本，缩短了制造时间并提高了产品的可靠性。

    Fabrication method of electronic package
    59.
    发明授权
    Fabrication method of electronic package 有权

    公开(公告)号：US10403567B2

    公开(公告)日：2019-09-03

    申请号：US15866144

    申请日：2018-01-09

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Mu-Hsuan Chan ,  Chieh-Yuan Chi

    IPC: H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56

    Abstract: A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield.

Patent Agency Ranking