公开(公告)号：US20240290831A1

公开(公告)日：2024-08-29

申请号：US18658333

申请日：2024-05-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexei Sadovnikov ,  Guruvayurappan S. Mathur

IPC: H01L29/06 ,  H01L21/265 ,  H01L21/761 ,  H01L29/66 ,  H01L29/73

CPC classification number: H01L29/0619 ,  H01L21/26513 ,  H01L21/761 ,  H01L29/66234 ,  H01L29/73

Abstract: A method includes implanting dopant of a first conductivity type into an epitaxial layer of semiconductor material to form first and second false collector regions adjacent to the surface of the epitaxial layer. The first false collector region is located laterally on a first side of a base region. The base region is formed within the epitaxial layer from dopant of a second conductivity type that is opposite the first conductivity type. The second false collector region is located laterally on a second side of the base region. The second side is opposite the first side of the base region. The base region is a base of a parasitic bipolar junction in an isolation region of an active semiconductor device.

公开(公告)号：US20240047387A1

公开(公告)日：2024-02-08

申请号：US18490866

申请日：2023-10-20

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Sheldon Douglas Haynie ,  Ujwal Radhakrishna

IPC: H01L23/64 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/647 ,  H01L29/401 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/66659 ,  H01L29/7835 ,  H01L2223/6672

Abstract: A microelectronic device includes a doped region of semiconductor material having a first region and an opposite second region. The microelectronic device is configured to provide a first operational potential at the first region and to provide a second operational potential at the second region. The microelectronic device includes field plate segments in trenches extending into the doped region. Each field plate segment is separated from the semiconductor material by a trench liner of dielectric material. The microelectronic device further includes circuitry electrically connected to each of the field plate segments. The circuitry is configured to apply bias potentials to the field plate segments. The bias potentials are monotonic with respect to distances of the field plate segments from the first region of the doped region.

公开(公告)号：US20240038579A1

公开(公告)日：2024-02-01

申请号：US17877964

申请日：2022-07-31

Applicant: Texas Instruments Incorporated

Inventor： Asad Haider ,  Hao Yang ,  Guruvayurappan Mathur ,  Alexei Sadovnikov ,  Abbas Ali ,  Umamaheswari Aghoram

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76229 ,  H01L29/0623

Abstract: An electronic device includes a semiconductor substrate and a semiconductor surface layer having a first conductivity type, as well as a buried layer, a deep trench structure and a shallow trench isolation structure, the semiconductor surface layer over the semiconductor substrate and having a top surface, the buried layer having an opposite second conductivity type between the semiconductor surface layer and the semiconductor substrate, the deep trench structure including a trench that extends through the semiconductor surface layer and into the buried layer, a dielectric liner on a sidewall of the trench from the semiconductor surface layer to the buried layer, and polysilicon that extends on the dielectric liner and fills the trench to the side of the semiconductor surface layer, the shallow trench isolation structure extends into the semiconductor surface layer, and the shallow trench isolation structure in contact with the deep trench structure.

公开(公告)号：US20220367388A1

公开(公告)日：2022-11-17

申请号：US17318556

申请日：2021-05-12

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Sheldon Douglas Haynie ,  Ujwal Radhakrishna

IPC: H01L23/64 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66

Abstract: A microelectronic device includes a doped region of semiconductor material having a first region and an opposite second region. The microelectronic device is configured to provide a first operational potential at the first region and to provide a second operational potential at the second region. The microelectronic device includes field plate segments in trenches extending into the doped region. Each field plate segment is separated from the semiconductor material by a trench liner of dielectric material. The microelectronic device further includes circuitry electrically connected to each of the field plate segments. The circuitry is configured to apply bias potentials to the field plate segments. The bias potentials are monotonic with respect to distances of the field plate segments from the first region of the doped region.

公开(公告)号：US11049967B2

公开(公告)日：2021-06-29

申请号：US16179445

申请日：2018-11-02

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Natalia Lavrovskaya

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L29/06

Abstract: An integrated circuit chip and a method of fabricating the IC chip to include a transistor having a thick gate oxide in combination with STI. The method provides a wafer for which a source region location, a drain contact region location, an extended drain region location and a gate region location have been defined and forms an STI structure overlying the extended drain region location. After growing a gate oxide layer over the gate region location and a portion of the extended drain region location, the method forms a gate structure on the gate oxide layer, the gate structure having a gap overlying the intersection of an edge of the STI structure with the gate oxide layer.

公开(公告)号：US10811543B2

公开(公告)日：2020-10-20

申请号：US16232322

申请日：2018-12-26

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Alexei Sadovnikov ,  Abbas Ali ,  Yanbiao Pan ,  Stefan Herzer

IPC: H01L21/02 ,  H01L29/94 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device with an isolation structure and a trench capacitor, each formed using a single resist mask for etching corresponding first and second trenches of different widths and different depths, with dielectric liners formed on the trench sidewalls and polysilicon filling the trenches and deep doped regions surrounding the trenches, including conductive features of a metallization structure that connect the polysilicon of the isolation structure trench to the deep doped region to form an isolation structure.

公开(公告)号：US20200227440A1

公开(公告)日：2020-07-16

申请号：US16829970

申请日：2020-03-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexei Sadovnikov ,  Jeffrey A. Babcock

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L27/082 ,  H01L29/66 ,  H01L29/732 ,  H01L29/10 ,  H01L23/535 ,  H01L29/735

Abstract: Complementary high-voltage bipolar transistors in silicon-on-insulator (SC) integrated circuits is disclosed. In one disclosed embodiment, a collector region is formed in an epitaxial silicon layer disposed over a buried insulator layer. A base region and an emitter are disposed over the collector region. An n-type region is formed under the buried insulator layer (BOX) by implanting donor impurity through the active region of substrate and BOX into a p-substrate. Later in the process flow this n-type region is connected from the top by doped poly-silicon plug and is biased at Vcc. In this case it will deplete lateral portion of PNP collector region and hence, will increase its BV.

公开(公告)号：US20200212229A1

公开(公告)日：2020-07-02

申请号：US16232322

申请日：2018-12-26

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Alexei Sadovnikov ,  Abbas Ali ,  Yanbiao Pan ,  Stefan Herzer

IPC: H01L29/94 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238

Abstract: A semiconductor device with an isolation structure and a trench capacitor, each formed using a single resist mask for etching corresponding first and second trenches of different widths and different depths, with dielectric liners formed on the trench sidewalls and polysilicon filling the trenches and deep doped regions surrounding the trenches, including conductive features of a metallization structure that connect the polysilicon of the isolation structure trench to the deep doped region to form an isolation structure.

公开(公告)号：US10522663B2

公开(公告)日：2019-12-31

申请号：US15999542

申请日：2018-08-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexei Sadovnikov ,  Doug Weiser ,  Mattias Erik Dahlstrom ,  Joel Martin Halbert

IPC: H01L29/66 ,  H01L29/808 ,  H01L29/10 ,  H01L21/265 ,  H01L21/324 ,  H01L23/535 ,  H01L29/06

Abstract: A method of forming an electronic device includes forming first, second and third doped regions at a surface of a semiconductor substrate. A first buried layer is located within the semiconductor substrate below the first, second and third doped regions. Fourth and fifth doped regions are laterally spaced apart along the substrate and extend from the surface of the substrate to the first buried layer, the first, second and third doped regions being located between the fourth and fifth doped regions. A second buried layer is formed within the substrate and between the fourth and fifth doped regions such that a first portion of the semiconductor substrate is located between the first buried layer and the second buried layer, and a second portion of the semiconductor substrate is located between the first, second and third doped regions and the second buried layer.

公开(公告)号：US20170345813A1

公开(公告)日：2017-11-30

申请号：US15679592

申请日：2017-08-17

Applicant: Texas Instruments Incorporated

Inventor： Andrew D. Strachan ,  Alexei Sadovnikov ,  Gang Xue ,  Dening Wang

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/861

CPC classification number: H01L27/0255 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/6609 ,  H01L29/66113 ,  H01L29/861 ,  H01L29/8618

Abstract: A low dynamic resistance, low capacitance diode of a semiconductor device includes a heavily-doped n-type substrate. A lightly-doped n-type layer 1 micron to 5 microns thick is disposed on the n-type substrate. A lightly-doped p-type layer 3 microns to 8 microns thick is disposed on the n-type layer. The low dynamic resistance, low capacitance diode, of the semiconductor device includes a p-type buried layer, with a peak dopant density above 1×1017 cm−3, extending from the p-type layer through the n-type layer to the n-type substrate. The low dynamic resistance, low capacitance diode also includes an n-type region disposed in the p-type layer, extending to a top surface of the p-type layer.