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公开(公告)号：US20220130839A1
公开(公告)日：2022-04-28
申请号：US17570345
申请日：2022-01-06
Inventor： Pin-Hong Chen , Yi-Wei Chen , Tzu-Chieh Chen , Chih-Chieh Tsai , Chia-Chen Wu , Kai-Jiun Chang , Yi-An Huang , Tsun-Min Cheng
IPC: H01L27/108
Abstract: A method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer, in which the second conductive layer above the substrate and the second conductive layer below the substrate comprise different thickness; and forming a third conductive layer on the second conductive layer to fill the trench.
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公开(公告)号：US11239241B2
公开(公告)日：2022-02-01
申请号：US16583268
申请日：2019-09-26
Inventor： Pin-Hong Chen , Yi-Wei Chen , Chih-Chieh Tsai , Tzu-Chieh Chen , Tsun-Min Cheng , Chi-Mao Hsu
IPC: H01L27/108 , H01L21/768
Abstract: A fabricating method of a semiconductive element includes providing a substrate, wherein an amorphous silicon layer covers the substrate. Then, a titanium nitride layer is provided to cover and contact the amorphous silicon layer. Later, a titanium layer is formed to cover the titanium nitride layer. Finally, a thermal process is performed to transform the titanium nitride layer into a nitrogen-containing titanium silicide layer.
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公开(公告)号：US11088023B2
公开(公告)日：2021-08-10
申请号：US15927106
申请日：2018-03-21
Inventor： Pin-Hong Chen , Chih-Chieh Tsai , Tzu-Chieh Chen , Kai-Jiun Chang , Chia-Chen Wu , Yi-An Huang , Tsun-Min Cheng , Yi-Wei Chen , Wei-Hsin Liu
IPC: H01L21/768 , H01L21/324 , H01L27/108 , H01L23/532 , H01L21/285
Abstract: A method of forming a semiconductor structure includes providing a material layer having a recess formed therein. A first tungsten metal layer is formed at a first temperature and fills the recess. An anneal process at a second temperature is then performed, wherein the second temperature is higher than the first temperature.
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公开(公告)号：US20200258889A1
公开(公告)日：2020-08-13
申请号：US16858729
申请日：2020-04-27
Inventor： Yi-Wei Chen , Pin-Hong Chen , Tsun-Min Cheng , Chun-Chieh Chiu
IPC: H01L27/108 , H01L21/285 , H01L21/3215 , H01L23/532
Abstract: A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following steps. A polysilicon layer is formed on a substrate. A sacrificial layer is formed on the polysilicon layer. An implantation process is performed on the sacrificial layer and the polysilicon layer. The sacrificial layer is removed. A metal stack is formed on the polysilicon layer. The present invention also provides another method of forming a bit line gate structure of a dynamic random access memory (DRAM) including the following steps. A polysilicon layer is formed on a substrate. A plasma doping process is performed on a surface of the polysilicon layer. A metal stack is formed on the surface of the polysilicon layer.
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公开(公告)号：US10685964B2
公开(公告)日：2020-06-16
申请号：US16028364
申请日：2018-07-05
Inventor： Chih-Chieh Tsai , Pin-Hong Chen , Tzu-Chieh Chen , Tsun-Min Cheng , Yi-Wei Chen , Hsin-Fu Huang , Chi-Mao Hsu , Shih-Fang Tzou
IPC: H01L27/108
Abstract: A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.
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Patent Agency Ranking
公开(公告)号：US20200020698A1
公开(公告)日：2020-01-16
申请号：US16583268
申请日：2019-09-26
Inventor： Pin-Hong Chen , Yi-Wei Chen , Chih-Chieh Tsai , Tzu-Chieh Chen , Tsun-Min Cheng , Chi-Mao Hsu
IPC: H01L27/108 , H01L21/768
Abstract: A fabricating method of a semiconductive element includes providing a substrate, wherein an amorphous silicon layer covers the substrate. Then, a titanium nitride layer is provided to cover and contact the amorphous silicon layer. Later, a titanium layer is formed to cover the titanium nitride layer. Finally, a thermal process is performed to transform the titanium nitride layer into a nitrogen-containing titanium silicide layer.
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公开(公告)号：US10475900B2
公开(公告)日：2019-11-12
申请号：US15869005
申请日：2018-01-11
Inventor： Kai-Jiun Chang , Tsun-Min Cheng , Chih-Chieh Tsai , Jui-Min Lee , Yi-Wei Chen , Chia-Lung Chang , Wei-Hsin Liu
IPC: H01L29/49 , H01L21/285 , H01L29/66 , H01L27/108 , H01L21/28
Abstract: A method for manufacturing a semiconductor device with a cobalt silicide film is provided in the present invention. The method includes the steps of providing a silicon structure with an interlayer dielectric formed thereon, forming a contact hole in the interlayer dielectric to expose the silicon structure, depositing a cobalt film on the exposed silicon structure at a temperature between 300° C.-400° C., wherein a cobalt protecting film is in-situ formed on the surface of the cobalt film, performing a rapid thermal process to transform the cobalt film into a cobalt silicide film, and removing untransformed cobalt film.
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公开(公告)号：US20190319107A1
公开(公告)日：2019-10-17
申请号：US15985730
申请日：2018-05-22
Inventor： Chun-Chieh Chiu , Pin-Hong Chen , Yi-Wei Chen , Tsun-Min Cheng , Chih-Chien Liu , Tzu-Chieh Chen , Chih-Chieh Tsai , Kai-Jiun Chang , Yi-An Huang , Chia-Chen Wu , Tzu-Hao Liu
IPC: H01L29/49 , H01L21/02 , H01L21/3213 , H01L21/28 , H01L29/423 , H01L27/108
Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.
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公开(公告)号：US10323332B2
公开(公告)日：2019-06-18
申请号：US15206321
申请日：2016-07-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Ling Lin , Yen-Liang Lu , Chi-Mao Hsu , Chin-Fu Lin , Chun-Hung Chen , Tsun-Min Cheng , Chi-Ray Tsai
IPC: C25D7/12 , C25D5/00 , C25D3/38 , C25D5/10 , C25D5/54 , H01L21/288 , H01L21/768
Abstract: An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure.
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公开(公告)号：US10199228B2
公开(公告)日：2019-02-05
申请号：US15479292
申请日：2017-04-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Nien-Ting Ho , Chien-Hao Chen , Hsin-Fu Huang , Chi-Yuan Sun , Wei-Yu Chen , Min-Chuan Tsai , Tsun-Min Cheng , Chi-Mao Hsu
IPC: H01L21/76 , H01L21/28 , H01L29/49 , H01L21/8238 , H01L29/51 , H01L29/66 , H01L29/78 , H01L29/165
Abstract: A manufacturing method of a metal gate structure includes the following steps. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. The silicon-containing work function layer includes a vertical portion and a horizontal portion. Finally, the gate trench is filled up with a conductive metal layer.
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