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    Fin structure and fin structure cutting process
    51.
    发明授权
    Fin structure and fin structure cutting process 有权
    翅片结构和翅片结构切割过程

    公开(公告)号：US09524909B2

    公开(公告)日：2016-12-20

    申请号：US14696494

    申请日：2015-04-27

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Tong-Jyun Huang ,  Rai-Min Huang ,  I-Ming Tseng ,  Kuan-Hsien Li ,  Chen-Ming Huang

    IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/02 ,  H01L27/088

    CPC classification number: H01L21/76224 ,  H01L21/02271 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653

    Abstract: A fin structure cutting process includes the following steps. Four fin structures are formed in a substrate, where the four fin structures including a first fin structure, a second fin structure, a third fin structure and a fourth fin structure are arranged sequentially and parallel to each other. A first fin structure cutting process is performed to remove top parts of the second fin structure and the third fin structure, thereby a first bump being formed from the second fin structure, and a second bump being formed from the third fin structure. A second fin structure cutting process is performed to remove the second bump and the fourth fin structure completely, but to preserve the first bump beside the first fin structure. Moreover, the present invention provides a fin structure formed by said process.

    Abstract translation: 翅片结构切割过程包括以下步骤。 在基板中形成有四个翅片结构，其中包括第一翅片结构，第二翅片结构，第三翅片结构和第四翅片结构的四个翅片结构彼此顺序并联。 执行第一鳍结构切割处理以去除第二鳍结构和第三鳍结构的顶部部分，从而由第二鳍结构形成第一凸起，以及由第三鳍结构形成的第二凸起。 执行第二鳍结构切割处理以完全去除第二凸起和第四鳍结构，但是将第一凸起保持在第一鳍结构旁边。 此外，本发明提供了一种通过所述方法形成的翅片结构。

    Semiconductor device having metal gate and manufacturing method thereof
    52.
    发明授权
    Semiconductor device having metal gate and manufacturing method thereof 有权
    具有金属栅极的半导体器件及其制造方法

    公开(公告)号：US08765591B2

    公开(公告)日：2014-07-01

    申请号：US14023482

    申请日：2013-09-11

    Applicant: United Microelectronics Corp.

    Inventor： Ssu-I Fu ,  I-Ming Tseng ,  En-Chiuan Liou ,  Cheng-Guo Chen

    IPC: H01L21/465

    CPC classification number: H01L29/66492 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

    Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having at least a dummy gate, a sacrificial layer covering sidewalls of the dummy gate and a dielectric layer exposing a top of the dummy gate formed thereon, forming a sacrificial layer covering sidewalls of the dummy gate on the substrate, forming a dielectric layer exposing a top of the dummy gate on the substrate, performing a first etching process to remove a portion of the sacrificial layer surrounding the top of the dummy gate to form at least a first recess, and performing a second etching process to remove the dummy gate to form a second recess. The first recess and the second recess construct a T-shaped gate trench.

    Abstract translation: 制造具有金属栅极的半导体器件的方法包括提供至少具有虚拟栅极的基板，覆盖伪栅极的侧壁的牺牲层和暴露其上形成的伪栅极顶部的电介质层，形成覆盖侧壁的牺牲层 形成在基板上暴露伪栅极的顶部的电介质层，执行第一蚀刻工艺以去除围绕虚拟栅极顶部的牺牲层的一部分，以形成至少第一凹部 ，并执行第二蚀刻处理以去除伪栅极以形成第二凹部。 第一凹部和第二凹部构成T形栅极沟槽。

    SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF
    53.
    发明申请
    SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF 有权
    具有金属门的半导体器件及其制造方法

    公开(公告)号：US20140017867A1

    公开(公告)日：2014-01-16

    申请号：US14023482

    申请日：2013-09-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ssu-I Fu ,  I-Ming Tseng ,  En-Chiuan Liou ,  Cheng-Guo Chen

    IPC: H01L29/66

    CPC classification number: H01L29/66492 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

    Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having at least a dummy gate, a sacrificial layer covering sidewalls of the dummy gate and a dielectric layer exposing a top of the dummy gate formed thereon, forming a sacrificial layer covering sidewalls of the dummy gate on the substrate, forming a dielectric layer exposing a top of the dummy gate on the substrate, performing a first etching process to remove a portion of the sacrificial layer surrounding the top of the dummy gate to form at least a first recess, and performing a second etching process to remove the dummy gate to form a second recess. The first recess and the second recess construct a T-shaped gate trench.

    Abstract translation: 制造具有金属栅极的半导体器件的方法包括提供至少具有虚拟栅极的基板，覆盖伪栅极的侧壁的牺牲层和暴露其上形成的伪栅极顶部的电介质层，形成覆盖侧壁的牺牲层 形成在基板上暴露伪栅极的顶部的电介质层，执行第一蚀刻工艺以去除围绕虚拟栅极顶部的牺牲层的一部分，以形成至少第一凹部 ，并执行第二蚀刻处理以去除伪栅极以形成第二凹部。 第一凹部和第二凹部构成T形栅极沟槽。

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