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公开(公告)号：US20190158029A1
公开(公告)日：2019-05-23
申请号：US16240601
申请日：2019-01-04
Applicant: pSemi Corporation
Inventor： Poojan Wagh , Kashish Pal , Robert Mark Englekirk , Tero Tapio Ranta , Keith Bargroff , Simon Edward Willard
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
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公开(公告)号：US20190121383A1
公开(公告)日：2019-04-25
申请号：US15793943
申请日：2017-10-25
Applicant: pSemi Corporation
Inventor： Robert Mark Englekirk , Keith Bargroff , Christopher C. Murphy , Tero Tapio Ranta
Abstract: A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit. A Current Digital to Analog Converter (IDAC) scales the output of the VWT and provides the scaled output to an amplifier bias input.
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公开(公告)号：US10250199B2
公开(公告)日：2019-04-02
申请号：US15268229
申请日：2016-09-16
Applicant: pSemi Corporation
Inventor： Jonathan Klaren , Poojan Wagh , David Kovac , Eric S. Shapiro , Neil Calanca , Dan William Nobbe , Christopher Murphy , Robert Mark Englekirk , Emre Ayranci , Keith Bargroff , Tero Tapio Ranta
Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.
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公开(公告)号：US20240402749A1
公开(公告)日：2024-12-05
申请号：US18736150
申请日：2024-06-06
Applicant: pSemi Corporation
Inventor： Robert Mark Englekirk , Keith Bargroff , Christopher C. Murphy , Tero Tapio Ranta
Abstract: A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit. A Current Digital to Analog Converter (IDAC) scales the output of the VWT and provides the scaled output to an amplifier bias input.
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公开(公告)号：US20240039479A1
公开(公告)日：2024-02-01
申请号：US18447207
申请日：2023-08-09
Applicant: pSemi Corporation
Inventor： Poojan Wagh , Kashish Pal , Robert Mark Englekirk , Tero Tapio Ranta , Keith Bargroff , Simon Edward Willard
CPC classification number: H03F1/0211 , H03F3/193 , H03F1/0261 , H03F1/223 , H03F2200/451 , H03F2200/21 , H03F2200/18 , H03F2200/522
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
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Patent Agency Ranking
公开(公告)号：US11720136B2
公开(公告)日：2023-08-08
申请号：US17987722
申请日：2022-11-15
Applicant: pSemi Corporation
Inventor： Robert Mark Englekirk , Keith Bargroff , Christopher C. Murphy , Tero Tapio Ranta
Abstract: A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit. A Current Digital to Analog Converter (IDAC) scales the output of the VWT and provides the scaled output to an amplifier bias input.
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公开(公告)号：US11664769B2
公开(公告)日：2023-05-30
申请号：US17843372
申请日：2022-06-17
Applicant: pSemi Corporation
Inventor： Jonathan James Klaren , David Kovac , Eric S. Shapiro , Christopher C. Murphy , Robert Mark Englekirk , Keith Bargroff , Tero Tapio Ranta
CPC classification number: H03F1/223 , H03F1/301 , H03F1/56 , H03F3/193 , H03F3/195 , H03F3/213 , H03F3/245 , H03F2200/102 , H03F2200/105 , H03F2200/165 , H03F2200/18 , H03F2200/21 , H03F2200/222 , H03F2200/225 , H03F2200/243 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/42 , H03F2200/451 , H03F2200/48 , H03F2200/489 , H03F2200/492 , H03F2200/498 , H03F2200/555 , H03F2200/61 , H03F2200/78
Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.
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公开(公告)号：US11451205B2
公开(公告)日：2022-09-20
申请号：US17124118
申请日：2020-12-16
Applicant: pSemi Corporation
Inventor： Tero Tapio Ranta , Keith Bargroff , Christopher C. Murphy , Robert Mark Englekirk
Abstract: Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain “droop” due to self-heating using a Sample and Hold (S&H) circuit. The S&H circuit samples and holds an initial temperature of the PA at commencement of a pulse. Thereafter, the S&H circuit generates a continuous measurement that corresponds to the temperature of the PA during the remainder of the pulse. A Gain Control signal is generated that is a function of the difference between the initial temperature and the operating temperature of the PA as the PA self-heats for the duration of the pulse. The Gain Control signal is applied to one or more adjustable or tunable circuits within a PA to offset the Gain droop of the PA.
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公开(公告)号：US20220158589A1
公开(公告)日：2022-05-19
申请号：US17531510
申请日：2021-11-19
Applicant: pSemi Corporation
Inventor： Poojan Wagh , Kashish Pal , Robert Mark Englekirk , Tero Tapio Ranta , Keith Bargroff , Simon Edward Willard
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
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公开(公告)号：US11054328B2
公开(公告)日：2021-07-06
申请号：US16294824
申请日：2019-03-06
Applicant: pSemi Corporation
Inventor： Vishnu Srinivasan , Ion Opris , Keith Bargroff
Abstract: Methods and devices to mitigate time varying impairments in sensors are described. The application of such methods and devices to pressure sensors facing time varying parasitic capacitances due to water droplets is detailed. Benefits of auto-zeroing technique as adopted in disclosed devices is also described.
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