公开(公告)号：US20130032822A1

公开(公告)日：2013-02-07

申请号：US13564779

申请日：2012-08-02

Applicant: Keiji ISHIBASHI

Inventor： Keiji ISHIBASHI

IPC: H01L29/24 ,  H01L21/304 ,  H01L21/20 ,  B32B3/02

CPC classification number: H01L21/304 ,  C30B23/025 ,  C30B29/36 ,  C30B33/00 ,  H01L21/02002 ,  H01L21/02008 ,  H01L21/0201 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02658 ,  H01L21/28 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/34 ,  H01L29/36 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7813 ,  Y10T428/21

Abstract: A substrate capable of achieving a lowered probability of defects produced in a step of forming an epitaxial film or a semiconductor element, a semiconductor device including the substrate, and a method of manufacturing a semiconductor device are provided. A substrate is a substrate having a front surface and a back surface, in which at least a part of the front surface is composed of single crystal silicon carbide, the substrate having an average value of surface roughness Ra at the front surface not greater than 0.5 nm, a standard deviation σ of that surface roughness Ra not greater than 0.2 nm, an average value of surface roughness Ra at the back surface not smaller than 0.3 nm and not greater than 10 nm, standard deviation σ of that surface roughness Ra not greater than 3 nm, and a diameter D of the front surface not smaller than 110 mm.

公开(公告)号：US20110011838A1

公开(公告)日：2011-01-20

申请号：US12458573

申请日：2009-07-16

Applicant: Shu-Ling Kuo

Inventor： Shu-Ling Kuo

IPC: B23K26/00 ,  B28D1/02 ,  B24B1/00

CPC classification number: B23K26/0006 ,  B23K26/3576 ,  B23K26/361 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/50 ,  B23K2103/56 ,  H01L21/0201 ,  H01L21/268 ,  Y02P70/605

Abstract: The present invention discloses a method for fabricating semiconductor wafers applicable to IC manufacture, which comprises steps: providing an ingot; slicing the ingot into a plurality of wafers; using a laser to illuminate the surface of the wafers to eliminate the saw marks generated by slicing and fuse the microcracks on the surface of the wafers; pickling, polishing and inspecting the wafers. The present invention uses intensive laser energy to remove saw marks generated by slicing and fuse microcracks generated by stress. Thereby, the effect of isotropic etching is reduced in the succeeding pickling procedures, and the damage layer is minimized. Thus, the thickness of the removed material is reduced, and a single ingot can be sliced into more wafers.

Abstract translation: 本发明公开了一种制造适用于IC制造的半导体晶片的方法，包括步骤：提供晶锭; 将锭切成多个晶片; 使用激光照射晶片的表面以消除通过切片并熔合晶片表面上的微裂纹而产生的锯痕; 酸洗，抛光和检查晶圆。 本发明使用强激光能量去除切片产生的锯痕并融合由应力产生的微裂纹。 因此，随后的酸洗过程中各向同性蚀刻的效果降低，损伤层被最小化。 因此，去除的材料的厚度减小，并且单个锭可以切成更多的晶片。

公开(公告)号：US20090242125A1

公开(公告)日：2009-10-01

申请号：US12409371

申请日：2009-03-23

Applicant: Young J. Paik ,  Melvin Barrentine ,  Abhijit Y. Desai ,  Hai Nguyen ,  Ashish Bhatnagar ,  Rajkumar Alagarsamy

Inventor： Young J. Paik ,  Melvin Barrentine ,  Abhijit Y. Desai ,  Hai Nguyen ,  Ashish Bhatnagar ,  Rajkumar Alagarsamy

IPC: C23F1/08 ,  C09K3/14 ,  F16J15/02 ,  B32B3/00 ,  B32B3/02

CPC classification number: H01L21/6838 ,  B24B37/30 ,  H01L21/0201 ,  H01L21/30625 ,  Y10T428/24355 ,  Y10T428/24612

Abstract: A method and apparatus for planarizing a substrate are provided. A substrate carrier head with an improved cover for holding the substrate securely is provided. The cover may have a bead that is larger than the recess into which it fits, such that the compression forms a conformal seal inside the recess. The bead may also be left uncoated to enhance adhesion of the bead to the surface of the groove. The surface of the cover may be roughened to reduce adhesion of the substrate to the cover without using a non-stick coating.

Abstract translation: 提供了一种用于平坦化基板的方法和装置。 提供了一种具有改进的用于固定基板的盖的基板载体头。 盖可以具有比其配合的凹部大的凸缘，使得压缩在凹部内形成共形密封。 胎圈也可以不涂覆以增强胎圈与沟槽表面的粘附。 盖的表面可以被粗糙化，以减少基材与盖的粘附，而不使用不粘涂层。

公开(公告)号：US4470856A

公开(公告)日：1984-09-11

申请号：US464442

申请日：1983-02-07

Applicant: Michael J. Little ,  Roger H. Brown ,  Uzi Efron ,  Clarence P. Hoberg

Inventor： Michael J. Little ,  Roger H. Brown ,  Uzi Efron ,  Clarence P. Hoberg

IPC: G01J1/02 ,  B21D22/10 ,  G01B11/26 ,  H01L20060101 ,  H01L21/302 ,  H01L21/66 ,  H01L31/02 ,  H01L31/0203 ,  H01L31/0232 ,  G01B11/06

CPC classification number: H01L21/0201 ,  G01B11/26 ,  H01L31/0203

Abstract: A semiconductive substrate, such as a silicon wafer, is mounted on a baseplate for inclusion in an optical device such as a liquid crystal light valve. An optical flat presses the top surface of silicon wafer toward the baseplate and against an O-ring seal surrounding a fluid adhesive. The fluid adhesive hydrostatically distributes the force of compression to guarantee optical flatness and self-compensation for the amount fluid adhesive surrounded by the O-ring. The optical flatness of the semiconductor substrate is limited only by the flatness of the optical flat against which it is compressed. Parallel alignment of the optical flat, the substrate and the baseplate is achieved by reflecting a laser beam through the semiconductive substrate and observing the interference fringes therein, while adjusting the relative alignment so as to maximize the distance between fringes.

Abstract translation: 诸如硅晶片的半导体基板安装在基板上以包含在诸如液晶光阀的光学装置中。 光学平面将硅晶片的顶表面压向底板并且抵靠围绕流体粘合剂的O形圈密封件。 流体粘合剂可以流体分配压缩力，以保证由O形环包围的流体粘合剂的光学平面度和自我补偿。 半导体衬底的光学平面度仅受到被压缩的光学平面的平坦度的限制。 通过将激光束反射通过半导体基片并观察其中的干涉条纹，同时调整相对对准以使条纹之间的距离最大化，来实现光学平面，基底和基板的平行对准。

公开(公告)号：US20240339315A1

公开(公告)日：2024-10-10

申请号：US18626490

申请日：2024-04-04

Applicant: GLOBALWAFERS JAPAN CO., LTD.

Inventor： Susumu MAEDA ,  Haruo SUDO ,  Hisashi MATSUMURA

IPC: H01L21/02

CPC classification number: H01L21/0201

Abstract: To provide a method of manufacturing silicon wafers having a low oxygen concentration and being provided with the gettering capability of heavy metals even when the density of BMD is low. The method includes a step of placing wafers sliced from a silicon single crystal and having an oxygen concentration in the range of 1×1016 atoms/cm3 to 7×1017 atoms/cm3, in a chamber and a step of performing rapid thermal processing at a maximum temperature reached of not less than 1250° C. or not more than 1350° C. after introducing a mixed gas having an oxygen partial pressure in the range of 1% to 10% of oxygen and an inert gas.

公开(公告)号：US11942349B2

公开(公告)日：2024-03-26

申请号：US17588985

申请日：2022-01-31

Applicant: MITSUI CHEMICALS TOHCELLO, INC.

Inventor： Eiji Hayashishita

IPC: H01L21/66 ,  C09J7/20 ,  C09J7/22 ,  C09J201/00 ,  H01L21/67 ,  H01L21/677 ,  H01L21/683 ,  B32B43/00 ,  G01R1/04 ,  G01R31/28 ,  H01L21/02

CPC classification number: H01L21/683 ,  C09J7/20 ,  C09J7/22 ,  C09J201/00 ,  H01L21/67092 ,  H01L21/67098 ,  H01L21/67721 ,  H01L21/6836 ,  B32B43/006 ,  C09J2203/326 ,  G01R1/0491 ,  G01R31/2831 ,  H01L21/0201

Abstract: Provided are a film for manufacturing semiconductor component, a film for electronic component manufacture, a method for manufacturing a semiconductor component using such a film for manufacturing semiconductor component, and a method for manufacturing an electronic component using such a film for electronic component manufacture. The film for component manufacture includes a base layer and an adhesive layer provided on one surface side of the base layer, and the Ra (μm) of the surface of one side of the base layer on which the adhesive layer is not provided is 0.1 to 2.0, and the Rz (μm) is 1.0 to 15. The method using the film for component manufacture includes a segmenting step, a pickup step, and an evaluation step prior to the pickup step.

公开(公告)号：US11883958B2

公开(公告)日：2024-01-30

申请号：US16434886

申请日：2019-06-07

Applicant: Applied Materials, Inc.

Inventor： Karuppasamy Muthukamatchy ,  Rajkumar Thanu ,  Eran Weiss ,  Jeffrey C. Hudgens ,  Chandrakant M. Sapkale

IPC: H01L21/677 ,  B25J9/00 ,  B25J9/10 ,  B25J9/16 ,  H01L21/02

CPC classification number: B25J9/0087 ,  B25J9/109 ,  B25J9/161 ,  H01L21/0201 ,  H01L21/02104 ,  H01L21/67742 ,  H01L21/67754

Abstract: A robot apparatus may include an upper arm adapted to rotate about a first rotational axis and a forearm rotatably coupled to the upper arm at a second rotational axis. A first wrist member may be rotatably coupled to the forearm at a third rotation axis. A second wrist member may be rotatably coupled to the forearm at the third rotation axis. A first end effector may be coupled to the first wrist member and a second end effector may be coupled to the second wrist member. The first wrist member and the second wrist member may be configured to rotate about the third rotational axis between a first pitch and a second pitch as a function of extension of the robot apparatus. Other apparatus and methods are disclosed.

公开(公告)号：US20230191619A1

公开(公告)日：2023-06-22

申请号：US18170962

申请日：2023-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Ti Wang ,  Chih-Wei Lin ,  Fu-Hsien Li ,  Yi-Ming Chen ,  Cheng-Ho Hung

IPC: B25J11/00 ,  G01B11/30 ,  H01L21/67

CPC classification number: B25J11/008 ,  G01B11/306 ,  H01L21/67005 ,  H01L21/0201

Abstract: A system includes a plurality of semiconductor processing tools; a carrier purge station; a carrier repair station; and an overhead transport (OHT) loop for transporting one or more substrate carriers among the plurality of semiconductor processing tools, the carrier purge station, and the carrier repair station. The carrier purge station is configured to receive a substrate carrier from one of the plurality of semiconductor processing tools, purge the substrate carrier with an inert gas, and determine if the substrate carrier needs repair. The carrier repair station is configured to receive a substrate carrier to be repaired and replace one or more parts in the substrate carrier.

公开(公告)号：US20180138353A1

公开(公告)日：2018-05-17

申请号：US15808561

申请日：2017-11-09

Applicant: Infineon Technologies AG

Inventor： Francisco Javier Santos Rodriguez ,  Roland Rupp ,  Hans-Joachim Schulze

IPC: H01L31/18 ,  H01L31/068 ,  H01L21/02 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L31/186 ,  H01L21/02008 ,  H01L21/0201 ,  H01L21/02167 ,  H01L21/02233 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/3178 ,  H01L31/068 ,  H01L31/1868

Abstract: A semiconductor ingot is sliced to obtain a semiconductor slice with a front side surface and a rear side surface parallel to the front side surface. A passivation layer is formed directly on at least one of the front side surface and the rear side surface. A barrier layer including least one of silicon carbide, a ternary nitride, and a ternary carbide is formed on the rear side surface.

公开(公告)号：US09601324B2

公开(公告)日：2017-03-21

申请号：US14798799

申请日：2015-07-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： I-Hsiung Huang ,  Heng-Hsin Liu ,  Heng-Jen Lee ,  Chin-Hsiang Lin

IPC: H01L21/02 ,  H01L21/683

CPC classification number: H01L21/0201 ,  H01L21/6835 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: A method including bonding a process wafer having integrated circuits and a carrier wafer having at least one alignment mark to form a wafer assembly. The method further includes aligning the wafer assembly using the at least one alignment mark of the carrier wafer.