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    Audio spectrum analyzer implemented with a minimum number of multiply operations
    62.
    发明申请
    Audio spectrum analyzer implemented with a minimum number of multiply operations 有权
    音频频谱分析仪采用最小数量的乘法运算

    公开(公告)号：US20030179820A1

    公开(公告)日：2003-09-25

    申请号：US09972558

    申请日：2001-10-08

    Applicant: Microchip Technology Inc.

    Inventor： Thomas J. Bombard

    IPC: H04Q001/20 ,  H04B003/46

    CPC classification number: G01R23/16

    Abstract: A spectrum analyzer that may be implemented by a simple microcontroller that does not have a hardware multiply function is disclosed. The spectrum analyzer of the present invention utilizes at least five frequency bins. The input signal is sampled at four times the bin frequency. The input signal is sampled at twice the Nyquist rate, which results in symmetries in the sin(wn) and cos(wn) functions. These symmetries allow the in-phase and quadrature components of the input signal to be calculated by add, ignore or subtract operations instead of the more complex multiplication and integration operations. Accordingly, the energy for each bin may be calculated with a minimum number of multiply operations. Because the number of multiply operations have been significantly reduced, these multiply operations may be performed by software instead of hardware. As a result, the spectrum analyzer may be implemented with a simple processor that does not have a hardware multiply. Another frequency bin is added by oversampling the highest frequency. A low pass filter is used to eliminate the effect of aliasing on the other frequency bins. A simple processor can still handle a bin that has been processed in this manner. As a result, at least five frequency bins may be processed by a spectrum analyzer implemented on a simple processor.

    Abstract translation: 公开了可以由不具有硬件乘法功能的简单微控制器实现的频谱分析仪。 本发明的频谱分析仪使用至少五个频率分
    组。 输入信号以四倍的频率采样。 输入信号以奈奎斯特速率的两倍采样，这导致sin（wn）和cos（wn）函数中的对称性。 这些对称性允许输入信号的同相和正交分量通过加法，忽略或减法运算而不是更复杂的乘法和积分运算来计算。 因此，可以用最小的乘法运算来计算每个仓的能量。 由于乘法运算的数量已经大大减少，所以这些乘法运算可以由软件代替硬件执行。 结果，频谱分析仪可以用不具有硬件乘法的简单处理器来实现。 通过过采样最高频率来添加另一个频率仓。 低通滤波器用于消除混叠对其他频率仓的影响。 一个简单的处理器仍然可以处理已经以这种方式处理的bin。 结果，至少五个频率仓可以由在简单处理器上实现的频谱分析仪处理。

    System and method for protecting contents of microcontroller memory by providing scrambled data in response to an unauthorized read access without alteration of the memory contents
    64.
    发明授权
    System and method for protecting contents of microcontroller memory by providing scrambled data in response to an unauthorized read access without alteration of the memory contents 失效
    通过在不改变存储器内容的情况下响应于未经授权的读取访问提供加密数据来保护微控制器存储器的内容的系统和方法

    公开(公告)号：US5446864A

    公开(公告)日：1995-08-29

    申请号：US207886

    申请日：1994-03-07

    Applicant: Martin Burghardt ,  Eric Berman ,  Ajay Padgaonkar ,  Ray Allen

    Inventor： Martin Burghardt ,  Eric Berman ,  Ajay Padgaonkar ,  Ray Allen

    IPC: G06F12/14

    CPC classification number: G06F12/1433

    Abstract: A microcontroller fabricated on a semiconductor chip has an on-chip EPROM program memory. The microcontroller is selectively configurable to operate in any one of a plurality of predetermined operating modes, including at least one secure microcontroller mode. A plurality of EPROM configuration fuses used for configuring the microcontroller and protecting its program memory from read, verify or write through any instruction initiated from other than a predetermined secure area of the chip, are mapped into the on-chip EPROM program memory as bits in respective address locations thereof. The value of a bit representing any one of said fuses is effective to determine the condition of the respective fuse. That condition is observed by reading the value of the respective bit for that fuse stored in the EPROM program memory. The chip security is enabled by configuring the microcontroller in a code protected mode by programming the bits representing the desired fuses in the EPROM program memory to effectively blow or erase each fuse according to the desired configuration.

    Abstract translation: 在半导体芯片上制造的微控制器具有片上EPROM程序存储器。 微控制器被选择性地配置为以多个预定操作模式中的任一种操作，包括至少一个安全微控制器模式。 用于配置微控制器并保护其程序存储器的多个EPROM配置保险丝不被从芯片的预定安全区域以外发起的任何指令的读取，验证或写入，被映射到片上EPROM程序存储器中，作为 各自的地址位置。 表示任何一个所述保险丝的位的值对于确定相应保险丝的状态是有效的。 通过读取存储在EPROM程序存储器中的该熔丝的相应位的值来观察该条件。 通过将代表EPROM程序存储器中所需保险丝的位编程为根据所需配置有效地吹扫或擦除每个保险丝，可以通过将代码保护模式中的微控制器配置为芯片安全性。

    On-chip register setting and clearing
    65.
    发明授权
    On-chip register setting and clearing 失效
    片上寄存器设置和清零

    公开(公告)号：US5033025A

    公开(公告)日：1991-07-16

    申请号：US454137

    申请日：1989-12-21

    Applicant: Ajay J. Padgaonkar

    Inventor： Ajay J. Padgaonkar

    IPC: G11C7/10 ,  G11C7/20

    CPC classification number: G11C7/1084 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/20

    Abstract: A semiconductor integrated circuit device has an on-chip processor and at least one on-chip digital register for storing plural bits therein. The bit contents of the register are written, selectively transformed, and read out of the register during processing of data by the processor and related circuitry. Peripheral instructions such as those from an interrupt source may contend with instructions from the processor for setting and clearing one or more bits in the register. To permit setting and clearing a unique bit in the register without affecting other bits in the register or the capability of the contending source to perform its instructions on one or more of these other bits, three separate addresses are provided for bit set, bit clear, and direct write of the register.

    Abstract translation: 半导体集成电路器件具有片上处理器和用于在其中存储多个位的至少一个片上数字寄存器。 在由处理器和相关电路处理数据期间，寄存器的位内容被写入，选择性地变换和从寄存器中读出。 来自中断源的外设指令可以与来自处理器的指令相抵触，用于设置和清除寄存器中的一个或多个位。 为了允许设置和清除寄存器中的唯一位，而不影响寄存器中的其他位或竞争源在其中一个或多个位上执行其指令的能力，为位置1，位清零提供三个单独的地址， 并直接写入寄存器。

    Regression neural network for identifying threshold voltages to be used in reads of flash memory devices
    66.
    发明授权
    Regression neural network for identifying threshold voltages to be used in reads of flash memory devices 有权

    公开(公告)号：US12175363B2

    公开(公告)日：2024-12-24

    申请号：US17089891

    申请日：2020-11-05

    Applicant: Microchip Technology Inc.

    Inventor： Lorenzo Zuolo ,  Rino Micheloni

    IPC: G06N3/08 ,  G06F3/06 ,  G06N3/04 ,  G06N5/04 ,  G06N20/00 ,  G11C11/54 ,  G11C16/26

    Abstract: A method and apparatus for reading a flash memory device are disclosed. A Regression Neural Network (RNN) inference model is stored on a flash controller. The RNN inference model is configured for identifying at least one Threshold-Voltage-Shift Read-Error (TVS-RE) curve that identifies a number of errors as a function of Threshold Voltage Shift Offset (TVSO) values. The operation of a flash memory device is monitored to identify usage characteristic values. A neural network operation of the RNN inference model is performed to generate a TVS-RE curve corresponding to the usage characteristic values. The input for the neural network operation includes the usage characteristic values. A TVSO value is identified corresponding to a minimum value of the TVS-RE curve. A read of the flash memory device is performed using a threshold-voltage-shift read at the TVSO value.

    Method and apparatus for decoding with trapped-block management
    68.
    发明授权
    Method and apparatus for decoding with trapped-block management 有权

    公开(公告)号：US11843393B2

    公开(公告)日：2023-12-12

    申请号：US17952240

    申请日：2022-09-24

    Applicant: Microchip Technology Inc.

    Inventor： Peter John Waldemar Graumann

    IPC: H03M13/11 ,  H03M13/00

    CPC classification number: H03M13/1111 ,  H03M13/611

    Abstract: A method and apparatus for decoding in which a first failed decode operation is performed on raw bit values of a FEC block by a LDPC decoder. When the FEC block is determined to be a trapped block an updated LLR map is generated; the updated LLR map and either the raw bit values of the FEC block or a failed-decode-output-block from a previous failed decode operation on the trapped block are provided to the LDPC decoder; a decode operation of the LDPC decoder is performed using the updated LLR map on the bit values of the FEC block or the failed-decode-output-block from the previous failed decode operation; and the generating, the providing and the performing are repeated until the decode operation is successful or until a predetermined number of trapped-block-decoding iterations have been performed. When the decode operation is successful in decoding the FEC block the codeword is output.

    Method and apparatus for carrying constant bit rate (CBR) client signals using CBR carrier streams comprising frames
    70.
    发明公开
    Method and apparatus for carrying constant bit rate (CBR) client signals using CBR carrier streams comprising frames 审中-公开

    公开(公告)号：US20230300047A1

    公开(公告)日：2023-09-21

    申请号：US18202899

    申请日：2023-05-27

    Applicant: Microchip Technology Inc.

    Inventor： Scott Muma ,  Winston Mok ,  Steven Scott GORSHE

    IPC: H04L43/062 ,  H04L43/0894

    CPC classification number: H04L43/062 ,  H04L43/0894

    Abstract: A method and apparatus in which a data stream is received that includes constant bit rate (CBR) carrier streams, at least one of which comprises frames, a cumulative phase offset report (CPOR) and a client rate report (CRR). A counter accumulating a PHY-scaled stream clock (IPSCk) is sampled at a nominal sampling period (Tps) to obtain a cumulative PHY-scaled count (CPSC). A PHY-scaled stream phase offset (PSPO) is calculated that indicates phase difference between PHY-scaled stream nominal bit count (LPSD) and an incoming PHY-scaled count delta (IPSD). The data stream is demultiplexed to obtain CBR carrier streams. Respective CBR carrier streams include a previous network node CPOR (CPOR-P) and a previous network node CPO (CPO-P). A CPO is calculated that is a function of CPO-P and PSPO. CPO-P is replaced with the calculated CPO. The CBR carrier streams are multiplexed into intermediate-network-node data streams that are transmitted from the intermediate-network-node.

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