公开(公告)号：US20050121671A1

公开(公告)日：2005-06-09

申请号：US11041178

申请日：2005-01-24

Applicant: Chia-Lin Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

Inventor： Chia-Lin Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

IPC: H01L21/20 ,  H01L21/28 ,  H01L21/30 ,  H01L29/49 ,  H01L29/78 ,  H01L29/04 ,  H01L29/10 ,  H01L31/036 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/02532 ,  H01L21/02595 ,  H01L21/2022 ,  H01L21/28035 ,  H01L21/3003 ,  H01L29/4925 ,  H01L29/78

Abstract: Within a method for forming a silicon layer, there is employed at least one sub-layer formed of a higher crystalline silicon material and at least one sub-layer formed of a lower crystalline silicon material. The lower crystalline silicon material is formed employing a hydrogen treatment of the higher crystalline silicon material. The method is particularly useful for forming polysilicon based gate electrodes with enhanced dimensional control and enhanced performance.

公开(公告)号：US20050106863A1

公开(公告)日：2005-05-19

申请号：US10712460

申请日：2003-11-13

Applicant: Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

Inventor： Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/44

CPC classification number: H01L21/02052 ,  Y10S438/906

Abstract: A method of manufacturing a semiconductor wafer including cleaning a surface of the wafer during a first time period and forming a layer over the surface during a second time period. The first time period includes a cleaning delay period prior to a cleaning portion of the first time period, the cleaning delay period configured such that an end time of the first time period substantially coincides with a start time of the second time period.

公开(公告)号：US06821868B2

公开(公告)日：2004-11-23

申请号：US10330850

申请日：2002-12-27

Applicant: Juing-Yi Cheng ,  T. L. Lee ,  Chia Lin Chen

Inventor： Juing-Yi Cheng ,  T. L. Lee ,  Chia Lin Chen

IPC: H01L21425

CPC classification number: H01L21/28202 ,  H01L21/28035 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/3115 ,  H01L21/3143 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/4925 ,  H01L29/518

Abstract: A method of forming a gate dielectric includes the steps of forming a gate oxide layer on a substrate, forming a buffer layer over the gate oxide layer and incorporating nitrogen into the gate oxide layer through the buffer layer. A semiconductor device having a gate structure is also provided. The gate includes a nitrogen enriched gate oxide layer formed on a substrate, a silicon nitride or poly-silicon buffer layer formed on the gate oxide layer and a gate electrode formed over the buffer layer.