公开(公告)号：US20060139694A1

公开(公告)日：2006-06-29

申请号：US11316125

申请日：2005-12-21

Applicant: Hideki Ishida ,  Chikara Ishihara ,  Shingo Yoshida

Inventor： Hideki Ishida ,  Chikara Ishihara ,  Shingo Yoshida

IPC: H04N1/40

CPC classification number: H04N1/40025 ,  H04N1/4015

Abstract: [Object]The object of this invention is to prevent as much as possible the occurrence of uneven image density produced by photoreceptors, in which uneven electrification and uneven sensitivity coexist, without enlargement of an apparatus as well as increase in cost. [Solution]For each of segments of the surface of the photoreceptor, individually memorizing a slope information K1 which defines the slope of when a pixel gradation is approximately linear-transformed into exposure amount, and then, based upon K1 per segment, individually transforming the pixel gradation into the exposure amount (individual exposure amount transformation). The slope information is an information which, with a reference electric potential Vs1, matches the electric potential after the exposure of when the exposure amount, obtained by transforming a reference pixel gradation Is1 by means of the individual exposure amount transformation, is applied to the approximately-linear exposure property excepting the converging region to a residual potential VL, or to the exposure property extending the aforesaid property by extrapolation operation, among exposure property g01 showing correspondence between the exposure amount and the electric potential after exposure per segment.

Abstract translation: 本发明的目的是尽可能地防止不均匀的电气化和不均匀的灵敏度共存的感光体产生的不均匀图像密度的产生，而不会增加设备的增加以及成本的增加。 [解决方案]对于感光体表面的每个段，分别存储限定像素级近似线性变换为曝光量的斜率的斜率信息K 1，然后基于每个段的K 1个别地 将像素等级变换为曝光量（个体曝光量变换）。 斜率信息是将参考电位Vs 1与曝光后的电位相匹配的信息，当将通过单独曝光量变换将参考像素灰度Is 1变换得到的曝光量应用于 在曝光量与暴露每段后的电位之间的对应关系的曝光特性g 01之中，通过外推操作将除会聚区域之外的残留电位VL的近似线性曝光特性或扩展上述性质的曝光性能。

公开(公告)号：US06844773B2

公开(公告)日：2005-01-18

申请号：US10613123

申请日：2003-07-07

Applicant: Hideki Ishida ,  Megumi Oono

Inventor： Hideki Ishida ,  Megumi Oono

IPC: H01L27/04 ,  G05F3/26 ,  H01L21/822 ,  H03F3/343 ,  H03F3/345 ,  H03F3/45 ,  H03K19/00 ,  G05F1/10

CPC classification number: G05F3/262 ,  H03F3/345 ,  H03F3/4521 ,  H03F2203/45658 ,  H03F2203/45702

Abstract: A semiconductor integrated circuit device has a first MIS transistor of a first conductivity type, a second MIS transistor of a second conductivity type, a resistor connected in series between a first power-source line and a second power-source line, and a third MIS transistor of the first conductivity type. The third MIS transistor has a gate connected to a node where the first MIS transistor and the second MIS transistor are connected together, and a drain connected to a connection node where the second MIS transistor and the resistor are connected together.

Abstract translation: 半导体集成电路器件具有第一导电类型的第一MIS晶体管，第二导电类型的第二MIS晶体管，串联连接在第一电源线和第二电源线之间的电阻器，以及第三MIS 第一导电类型的晶体管。 第三MIS晶体管具有连接到第一MIS晶体管和第二MIS晶体管连接在一起的节点的栅极，以及连接到第二MIS晶体管和电阻器连接在一起的连接节点的漏极。

公开(公告)号：US06624706B2

公开(公告)日：2003-09-23

申请号：US09988618

申请日：2001-11-20

Applicant: Hirohito Higashi ,  Hideki Ishida

Inventor： Hirohito Higashi ,  Hideki Ishida

IPC: H03L706

CPC classification number: H03L7/0805 ,  H03L1/022 ,  H03L7/0893 ,  H03L7/10 ,  H03L7/189

Abstract: A bias current IB additionally provided to a current-controlled circuit 13 in a PLL circuit is the sum of bias currents IB1 and IB2 which are generated by a bias adjustment circuit (18, 19, 20, 21 and 22) and a bias current generating circuit (23 and 24), respectively. The bias adjustment circuit adjusts the bias current IB1 in response to an adjustment start signal ADJ such that a control voltage VC converges to a reference voltage VREF, and ceases the adjustment when the convergence has been achieved. The reference voltage VREF is determined to be a value at an almost middle point in a range of the variable VC in the PLL circuit. The bias current generating circuit has a circuit 23 generating a bias voltage VT and a circuit 24 converting the VT into a current IB2, wherein the temperature characteristic of the bias voltage VT is reverse to that of the control voltage VC under the condition that the frequency of an oscillation signal OCLK is fixed.

公开(公告)号：US06374073B1

公开(公告)日：2002-04-16

申请号：US09882254

申请日：2001-06-18

Applicant: Akihiro Ozaki ,  Hideki Ishida

Inventor： Akihiro Ozaki ,  Hideki Ishida

IPC: G03G1501

Abstract: An image forming machine comprising image bearing means, charging means, exposure means, reversal development means, transfer means, and cleaning means. The transfer means includes a rotationally driven transfer belt, and transfer voltage applicator means for applying a transfer voltage to the back side of the transfer belt. The transfer voltage applicator means applies the transfer voltage to the transfer belt over a predetermined effective transfer width. The face side of the transfer belt is brought into contact with the image bearing means via an image receiving member and directly over a predetermined effective contact width. The effective contact width is larger than an effective charging width and larger than the effective transfer width.

公开(公告)号：US06311139B1

公开(公告)日：2001-10-30

申请号：US09061088

申请日：1998-04-16

Applicant: Takao Kuroda ,  Hideki Ishida

Inventor： Takao Kuroda ,  Hideki Ishida

IPC: G06F1500

CPC classification number: H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The necessary information such as chip area A, number of elements, and defect density D is inputted to calculate element density TD and mean element density TDM. The inverse operation chip area A′ is calculated from the estimation equation: Y=f(A) such as Stapper's equation showing the dependence of the yield on the defect density D and chip area A. Next, for various kinds of integrated circuit devices in a diffusion process, the functional relation g (TD/TDM) which is considered to be most correct is determined from the data of the relationship between the ratio (A′/A) and the ratio (TD/TDM), and from the relational expression g (TD/TDM), the correction factor K is calculated. Finally, the values of the correction factor K and the chip area A are substituted into Y=f(A×K) to calculate the expected yield Y.

Abstract translation: 输入芯片面积A，元件数量和缺陷密度D等必要的信息来计算元件密度TD和平均元件密度TDM。 根据估计方程：Y = f（A）计算反向运算芯片面积A'，例如显示产量对缺陷密度D和芯片面积A的依赖性的Stapper方程。接下来，对于各种集成电路器件 考虑到扩散过程，从比率（A'/ A）和比率（TD / TDM）之间的关系的数据中确定被认为是最正确的功能关系g（TD / TDM），并且从关系 表达式g（TD / TDM），计算校正因子K. 最后，将校正因子K和芯片面积A的值代入Y = f（AxK）来计算预期的产量Y.

公开(公告)号：US06194955B1

公开(公告)日：2001-02-27

申请号：US09283298

申请日：1999-04-01

Applicant: Hideki Ishida

Inventor： Hideki Ishida

IPC: G05F110

CPC classification number: H03K4/06 ,  H03K17/04106

Abstract: A current source switch circuit has at least one transistor forming part of a current source, and one switch for controlling the supply of an electric current from the transistor to a load. A voltage application unit applies a voltage having a value in an operation state as a current source to a transistor forming part of the current source while no electric current is provided from the switch to the load.

Abstract translation: 电流源开关电路具有形成电流源的一部分的至少一个晶体管和用于控制从晶体管到负载的电流的供应的一个开关。 电压施加单元将作为电流源的具有工作状态的值的电压施加到形成电流源的一部分的晶体管，同时没有从开关向负载提供电流。

公开(公告)号：US20080273153A1

公开(公告)日：2008-11-06

申请号：US12113515

申请日：2008-05-01

Applicant: Kentarou TAKEDA ,  Takeharu KITAGAWA ,  Daisuke HAYASHI ,  Hideki ISHIDA ,  Nao MURAKAMI ,  Junichi NAGASE

Inventor： Kentarou TAKEDA ,  Takeharu KITAGAWA ,  Daisuke HAYASHI ,  Hideki ISHIDA ,  Nao MURAKAMI ,  Junichi NAGASE

IPC: G02F1/13363

CPC classification number: G02F1/133634 ,  G02F1/1393 ,  G02F2001/133635 ,  G02F2413/02

Abstract: The liquid crystal panel according to an embodiment of the present invention includes, in the stated order from a viewer side: a first polarizer; a first optical compensation layer; a liquid crystal cell; a second optical compensation layer; and a second polarizer, wherein: the first optical compensation layer has an absolute value of a photoelastic coefficient of 40×10−12 (m2/N) or less, has an in-plane retardation Δnd of 90 nm to 200 nm, has relationships of the following Expressions (1) and (2), and functions as a protective layer on a liquid crystal cell side of the first polarizer; and the second optical compensation layer has relationships of the following Expressions (3) and (4), Δnd(380)=Δnd(550)=Δnd(780)   (1) nx>ny>nz   (2) Rth(380)>Rth(550)>Rth(780)   (3) nx=ny>nz.   (4)

Abstract translation: 根据本发明实施例的液晶面板按照从观察者侧的顺序包括：第一偏振器; 第一光学补偿层; 液晶单元; 第二光学补偿层; 和第二偏振器，其中：所述第一光学补偿层的光弹性系数的绝对值为40×12 -12（m 2 / N 2 / N）以下，具有in 平面延迟90nm〜200nm的色差具有以下表达式（1）和（2）的关系，并且用作第一偏振器的液晶单元侧的保护层; 并且第二光学补偿层具有以下表达式（3）和（4）的关系：<？in-line-formula description =“In-line Formulas”end =“lead”？> Deltand（380）= Deltand（550 ）= Deltand（780）（1）<？in-line-formula description =“In-line Formulas”end =“tail”？> <？in-line-formula description =“In-line Formulas”end =“lead “？> nx> ny> nz（2）<？in-line-formula description =”In-line Formulas“end =”tail“？> <？in-line-formula description =”In-line Formulas“end = “lead”→Rth（380）> Rth（550）> Rth（780）（3）<？in-line-formula description =“In-line Formulas”end =“tail”？> <？in-line- 公式description =“在线公式”end =“lead”？> nx = ny> nz。 （4）<？in-line-formula description =“In-line Formulas”end =“tail”？>

公开(公告)号：US07203860B2

公开(公告)日：2007-04-10

申请号：US10405243

申请日：2003-04-03

Applicant: Hideki Ishida ,  Masaaki Kaneko

Inventor： Hideki Ishida ,  Masaaki Kaneko

IPC: G06F1/00 ,  G06F1/04 ,  G06F1/24 ,  G06F11/00

CPC classification number: H03K5/1565 ,  H03L7/0812 ,  H04L7/033

Abstract: A clock recovery circuit has a phase comparator circuit, a phase adjusting circuit, and a duty cycle correction circuit. The phase comparator circuit carries out phase comparison between an input signal and an output signal, and outputs a phase control signal proportional to a phase difference between the input signal and the output signal. The phase adjusting circuit receives the phase control signal from the phase comparator circuit, adjusts the phase of the input signal, and produces the output signal, and the duty cycle correction circuit receives the output signal from the phase adjusting circuit, and corrects the duty cycle of the output signal.

Abstract translation: 时钟恢复电路具有相位比较器电路，相位调整电路和占空比校正电路。 相位比较器电路在输入信号和输出信号之间进行相位比较，并输出与输入信号和输出信号之间的相位差成比例的相位控制信号。 相位调整电路从相位比较电路接收相位控制信号，调整输入信号的相位，产生输出信号，占空比校正电路从相位调整电路接收输出信号，校正占空比 的输出信号。

公开(公告)号：US07116744B2

公开(公告)日：2006-10-03

申请号：US09978726

申请日：2001-10-18

Applicant: Takuya Saze ,  Hirotaka Tamura ,  Takaya Chiba ,  Kohtaroh Gotoh ,  Hideki Ishida

Inventor： Takuya Saze ,  Hirotaka Tamura ,  Takaya Chiba ,  Kohtaroh Gotoh ,  Hideki Ishida

IPC: H04L25/00 ,  H03L7/06

CPC classification number: G11C7/1087 ,  G11C7/1078 ,  G11C7/222 ,  H03L7/0812 ,  H03L7/091 ,  H04L7/033 ,  H04L7/0337

Abstract: A clock recovery circuit has a boundary detection/discrimination circuit to detect and discriminate a boundary in an input signal in accordance with a first signal. The clock recovery circuit performs clock recovery by controlling the timing of the first signal in accordance with the detected boundary, wherein boundary detection timing in the boundary detection/discrimination circuit is varied by controlling the first signal.

公开(公告)号：US07110245B2

公开(公告)日：2006-09-19

申请号：US10533524

申请日：2004-04-09

Applicant: Hideki Ishida ,  Eizo Fujii ,  Yasuhiro Kishimoto ,  Hitoshi Ibuta

Inventor： Hideki Ishida ,  Eizo Fujii ,  Yasuhiro Kishimoto ,  Hitoshi Ibuta

IPC: H01G4/228 ,  H01G9/10

CPC classification number: H01G9/012 ,  H05K3/3442 ,  H05K2201/09381 ,  H05K2201/09663 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613

Abstract: The present invention provides a solid electrolytic capacitor comprising a capacitor element in which a dielectric coating layer and a cathode layer are sequentially formed on a surface of an anode element having an anode lead member planted on one end surface thereof, an anode terminal connected with the anode lead member, a platy cathode terminal mounting the capacitor element thereon and connected with the cathode layer, and an enclosure resin coating the capacitor element, a part of the cathode terminal and a part of the anode terminal being exposed on a same plane from the enclosure resin. The cathode terminal is provided with a cathode exposed portion exposed from the enclosure resin in at least two locations on the same plane.

Abstract translation: 本发明提供一种固体电解电容器，其包括电容器元件，其中在其一端表面上具有阳极引线构件的阳极元件的表面上依次形成电介质涂层和阴极层，阳极端子与 阳极引线构件，将电容器元件安装在其上并与阴极层连接的板状阴极端子，以及涂覆电容器元件的封装树脂，阴极端子的一部分和阳极端子的一部分在同一平面上从 外壳树脂。 阴极端子设置有在同一平面上的至少两个位置处从外壳树脂露出的阴极暴露部分。