公开(公告)号：US08476763B2

公开(公告)日：2013-07-02

申请号：US13237514

申请日：2011-09-20

Applicant: Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

Inventor： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

IPC: H01L23/48 ,  H01L21/4763 ,  H01L27/10 ,  H01L21/3205 ,  H01L21/768 ,  G06F17/50

CPC classification number: H01L21/2885 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.

Abstract translation: 形成导电图案结构的方法在被部分蚀刻以形成延伸到电池块的两端部的第一沟槽的衬底上形成绝缘中间层。 绝缘中间层也被部分蚀刻以形成与第一沟槽相邻的第二沟槽，以及延伸到电池块的两端部分的第三沟槽。 第二沟槽在电池块的中间部分具有断开的形状。 在绝缘中间层上形成种子铜层。 第一，第二和第三沟槽的内部部分用铜层电镀。 抛光铜层以暴露绝缘中间层，以分别在第一和第二沟槽中形成第一和第二导电图案，并在第三沟槽中形成第一虚设导电图案。 还描述了相关的导电图案结构。

公开(公告)号：US20130012023A1

公开(公告)日：2013-01-10

申请号：US13533653

申请日：2012-06-26

Applicant: In-sun Park ,  Gil-heyun Choi ,  Ji-soon Park ,  Jong-myeong Lee ,  Jong-won Hong ,  Hei-seung Kim

Inventor： In-sun Park ,  Gil-heyun Choi ,  Ji-soon Park ,  Jong-myeong Lee ,  Jong-won Hong ,  Hei-seung Kim

IPC: H01L21/308

CPC classification number: H01L23/48 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76816 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/06 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to example embodiments, a method of forming micropatterns includes forming dummy patterns having first widths on a dummy region of a substrate, and forming cell patterns having second widths on an active line region of the substrate. The active line region may be adjacent to the dummy region and the second widths may be less than the first widths. The method may further include forming damascene metallization by forming a seed layer on the active line region and the dummy region, forming a conductive material layer on a whole surface of the substrate, and planarizing the conductive material layer to form metal lines.

Abstract translation: 根据示例性实施例，形成微图案的方法包括在衬底的虚拟区域上形成具有第一宽度的虚拟图案，并且在衬底的有源线区域上形成具有第二宽度的单元图案。 有源线区域可以与虚拟区域相邻，并且第二宽度可以小于第一宽度。 该方法可以进一步包括通过在有源线区域和虚拟区域上形成种子层来形成镶嵌金属化，在基片的整个表面上形成导电材料层，并平坦化导电材料层以形成金属线。

公开(公告)号：US20130005154A1

公开(公告)日：2013-01-03

申请号：US13444054

申请日：2012-04-11

Applicant: Woo-Jin LEE ,  Ji-Soon PARK ,  Jong-Myeong LEE ,  Hyun-Bae LEE

Inventor： Woo-Jin LEE ,  Ji-Soon PARK ,  Jong-Myeong LEE ,  Hyun-Bae LEE

IPC: H01L21/316 ,  H01L21/318

CPC classification number: H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/02359 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of forming a dielectric layer, the method including sequentially forming a first oxide layer, a nitride layer, and a second oxide layer on a substrate by performing a plasma-enhanced atomic layer deposition process, wherein a first nitrogen plasma treatment is performed after forming the first oxide layer.

Abstract translation: 一种形成电介质层的方法，所述方法包括通过执行等离子体增强原子层沉积工艺在衬底上顺序地形成第一氧化物层，氮化物层和第二氧化物层，其中第一氮等离子体处理在 形成第一氧化物层。

公开(公告)号：US08324055B2

公开(公告)日：2012-12-04

申请号：US13044703

申请日：2011-03-10

Applicant: Pil-Kyu Kang ,  Dae-Lok Bae ,  Gil-Heyun Choi ,  Jong-Myeong Lee

Inventor： Pil-Kyu Kang ,  Dae-Lok Bae ,  Gil-Heyun Choi ,  Jong-Myeong Lee

IPC: H01L21/30 ,  H01L21/46

CPC classification number: H01L21/76254 ,  H01L21/743 ,  H01L21/84 ,  H01L27/10817 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/1203

Abstract: A method of manufacturing a buried wiring type substrate comprises implanting hydrogen ions into a single crystalline substrate through a first surface thereof to form an ion implantation region, forming a conductive layer comprising a metal on the first surface of the single crystalline substrate, forming an insulation layer comprising silicon oxide on the conductive layer, bonding the insulation layer to a support substrate to form a preliminary buried wiring type substrate, and separating the single crystalline substrate at the ion implantation region to form a single crystalline semiconductor layer on the conductive layer.

Abstract translation: 一种掩埋布线型衬底的制造方法，包括通过其第一表面将氢离子注入单晶衬底以形成离子注入区，在单晶衬底的第一表面上形成包含金属的导电层，形成绝缘层 在导电层上包含氧化硅的层，将绝缘层粘合到支撑衬底上以形成预埋掩埋布线型衬底，并且在离子注入区域处分离单晶衬底，以在导电层上形成单晶半导体层。

公开(公告)号：US20120193792A1

公开(公告)日：2012-08-02

申请号：US13237514

申请日：2011-09-20

Applicant: Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

Inventor： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/2885 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.

Abstract translation: 形成导电图案结构的方法在被部分蚀刻以形成延伸到电池块的两端部的第一沟槽的衬底上形成绝缘中间层。 绝缘中间层也被部分蚀刻以形成与第一沟槽相邻的第二沟槽，以及延伸到电池块的两端部分的第三沟槽。 第二沟槽在电池块的中间部分具有断开的形状。 在绝缘中间层上形成种子铜层。 第一，第二和第三沟槽的内部部分用铜层电镀。 抛光铜层以暴露绝缘中间层，以分别在第一和第二沟槽中形成第一和第二导电图案，并在第三沟槽中形成第一虚设导电图案。 还描述了相关的导电图案结构。

公开(公告)号：US20120009781A1

公开(公告)日：2012-01-12

申请号：US13240109

申请日：2011-09-22

Applicant: Kyung-In Choi ,  Hyeon-Deok Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee

Inventor： Kyung-In Choi ,  Hyeon-Deok Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee

IPC: H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76856 ,  H01L27/11526 ,  H01L27/11543 ,  H01L27/11546 ,  H01L27/11548

Abstract: In a method of manufacturing a metal wiring structure, a first metal wiring and a first barrier layer are formed on a substrate, and the first barrier layer is nitridated. An insulating interlayer is formed on the substrate so as to extend over the first metal wiring and the first barrier layer. Part of the insulating interlayer is removed to form a hole exposing at least part of the first metal wiring and part of the first barrier layer. A nitridation plasma treatment is performed on the exposed portion of the first barrier layer. A second barrier layer is formed along the bottom and sides of the hole. A plug is formed on the second barrier layer to fill the hole.

Abstract translation: 在制造金属布线结构的方法中，在基板上形成第一金属布线和第一阻挡层，并且对第一阻挡层进行氮化。 绝缘中间层形成在基板上，以便延伸越过第一金属布线和第一阻挡层。 去除部分绝缘中间层以形成露出第一金属布线和第一阻挡层的一部分的至少一部分的孔。 在第一阻挡层的暴露部分上进行氮化等离子体处理。 沿着孔的底部和侧面形成第二阻挡层。 在第二阻挡层上形成插塞以填充孔。

公开(公告)号：US20110250738A1

公开(公告)日：2011-10-13

申请号：US13082861

申请日：2011-04-08

Applicant: Pil-Kyu Kang ,  Dae-Lok Bae ,  Gil-Heyun Choi ,  Jong-Myeong Lee

Inventor： Pil-Kyu Kang ,  Dae-Lok Bae ,  Gil-Heyun Choi ,  Jong-Myeong Lee

IPC: H01L21/20 ,  C03C15/00 ,  G02B6/10

CPC classification number: H01L21/02381 ,  G02B6/13 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02675

Abstract: A method of forming a silicon based optical waveguide can include forming a silicon-on-insulator structure including a non-crystalline silicon portion and a single crystalline silicon portion of an active silicon layer in the structure. The non-crystalline silicon portion can be replaced with an amorphous silicon portion and maintaining the single crystalline silicon portion and the amorphous portion can be crystallized using the single crystalline silicon portion as a seed to form a laterally grown single crystalline silicon portion including the amorphous and single crystalline silicon portions.

Abstract translation: 形成硅基光波导的方法可以包括在该结构中形成包括非晶硅部分和活性硅层的单晶硅部分的绝缘体上硅结构。 可以用非晶硅部分替代非晶硅部分，并且使用单晶硅部分作为种子来保持单晶硅部分和非晶部分可以结晶，以形成横向生长的单晶硅部分，其包括非晶态和 单晶硅部分。

公开(公告)号：US20110223725A1

公开(公告)日：2011-09-15

申请号：US13044703

申请日：2011-03-10

Applicant: Pil-Kyu KANG ,  Dae-Lok BAE ,  Gil-Heyun CHOI ,  Jong-Myeong LEE

Inventor： Pil-Kyu KANG ,  Dae-Lok BAE ,  Gil-Heyun CHOI ,  Jong-Myeong LEE

IPC: H01L21/336 ,  H01L21/762

CPC classification number: H01L21/76254 ,  H01L21/743 ,  H01L21/84 ,  H01L27/10817 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/1203

Abstract: A method of manufacturing a buried wiring type substrate comprises implanting hydrogen ions into a single crystalline substrate through a first surface thereof to form an ion implantation region, forming a conductive layer comprising a metal on the first surface of the single crystalline substrate, forming an insulation layer comprising silicon oxide on the conductive layer, bonding the insulation layer to a support substrate to form a preliminary buried wiring type substrate, and separating the single crystalline substrate at the ion implantation region to form a single crystalline semiconductor layer on the conductive layer.

Abstract translation: 一种掩埋布线型衬底的制造方法，包括通过其第一表面将氢离子注入单晶衬底以形成离子注入区，在单晶衬底的第一表面上形成包含金属的导电层，形成绝缘层 在导电层上包含氧化硅的层，将绝缘层粘合到支撑衬底上以形成预埋掩埋布线型衬底，并且在离子注入区域处分离单晶衬底，以在导电层上形成单晶半导体层。

公开(公告)号：US07842600B2

公开(公告)日：2010-11-30

申请号：US12364598

申请日：2009-02-03

Applicant: Jong-ho Yun ,  Jong-Myeong Lee ,  Gil-heyun Choi

Inventor： Jong-ho Yun ,  Jong-Myeong Lee ,  Gil-heyun Choi

IPC: H01L21/4763

CPC classification number: H01L21/7682 ,  H01L21/76849 ,  H01L2224/05026 ,  H01L2224/05639 ,  H01L2224/05669 ,  H01L2224/13 ,  H01L2924/00014 ,  H01L2224/05099

Abstract: Methods of forming an interlayer dielectric having an air gap are provided including forming a first insulating layer on a semiconductor substrate. The first insulating layer defines a trench. A metal wire is formed in the trench such that the metal wire is recessed beneath an upper surface of the first insulating layer. A metal layer is formed on the metal wire, wherein the metal layer includes a capping layer portion filling the recess, a upper portion formed on the capping layer portion, and an overhang portion formed on the portion of the first insulating layer adjacent to the trench protruding sideward from the upper portion. The first insulating layer is removed and a second insulating layer is formed on the semiconductor substrate to cover the metal layer, whereby an air gap is formed below the overhang portion of the metal layer. A portion of the second insulating layer is removed to expose the upper portion of the metal layer. The upper portion and the overhang portion of the metal layer are removed. A third insulating layer is formed on the semiconductor substrate from which the upper portion and the overhang portion have been removed to maintain the air gap.

Abstract translation: 提供了形成具有气隙的层间电介质的方法，包括在半导体衬底上形成第一绝缘层。 第一绝缘层限定沟槽。 在沟槽中形成金属线，使得金属线在第一绝缘层的上表面下方凹入。 在金属线上形成金属层，其中金属层包括填充凹部的覆盖层部分，形成在覆盖层部分上的上部，和形成在与沟槽相邻的第一绝缘层的部分上的突出部分 从上部侧向突出。 去除第一绝缘层，并且在半导体衬底上形成覆盖金属层的第二绝缘层，由此在金属层的伸出部分的下方形成气隙。 去除第二绝缘层的一部分以露出金属层的上部。 去除金属层的上部和外伸部分。 在半导体基板上形成第三绝缘层，从该基板上去除上部和外伸部分以保持气隙。

公开(公告)号：US07833855B2

公开(公告)日：2010-11-16

申请号：US11474544

申请日：2006-06-26

Applicant: Sang-Bom Kang ,  Kyung-In Choi ,  You-Kyoung Lee ,  Seong-Geon Park ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Woo Lee

Inventor： Sang-Bom Kang ,  Kyung-In Choi ,  You-Kyoung Lee ,  Seong-Geon Park ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Woo Lee

IPC: H01L21/8238

CPC classification number: H01L29/6659 ,  C23C16/34 ,  C23C16/56 ,  H01L21/265 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/28556 ,  H01L21/76841 ,  H01L21/823425 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/7833

Abstract: In a method for forming a field effect transistor, a metal nitride layer is formed on a gate electrode insulating layer. Tantalum amine derivatives represented by the chemical formula Ta(NR1)(NR2R3)3, in which R1, R2 and R3 represent H or a C1-C6 alkyl group, may be used to form the metal nitride layer. Nitrogen may then be implanted into the metal nitride layer to increase the nitrogen content of the layer.

Abstract translation: 在形成场效应晶体管的方法中，在栅电极绝缘层上形成金属氮化物层。 可以使用由化学式Ta（NR1）（NR2R3）3表示的钽胺衍生物，其中R1，R2和R3代表H或C1-C6烷基，形成金属氮化物层。 然后可以将氮气注入到金属氮化物层中以增加该层的氮含量。