公开(公告)号：US12183715B2

公开(公告)日：2024-12-31

申请号：US17546283

申请日：2021-12-09

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ting-Cih Kang ,  Hsih-Yang Chiu

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure employing a via structure. The method includes forming a first conductive pad on a first semiconductor device; forming a second conductive pad on the first conductive pad; connecting a second semiconductor device to the first semiconductor device; and forming a via structure in the second semiconductor device, The via structure contacts the second conductive pad, and the first conductive pad and the second conductive pad are formed of different metal materials.

公开(公告)号：US12183643B2

公开(公告)日：2024-12-31

申请号：US17848514

申请日：2022-06-24

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Tzu-Ching Tsai

IPC: G06N3/08 ,  H01L21/66 ,  H01L21/67

Abstract: The present application discloses an implanting system. The implanting system includes an etch module executing a first implanting recipe on a first wafer to turn a first wafer state of the first wafer to a second wafer state; a first measurement module collecting the second wafer state of the first wafer to generate a first set of data; and an artificial intelligence module coupled to the first measurement module and the etch module, analyzing the first set of data and update the first implanting recipe to a second implanting recipe when the first set of data is not within a predetermined range. The artificial intelligence module is configured for generating the second implanting recipe taking into consideration at least one of an implanting rate of the second wafer, a rate of rotation of the second wafer, and a tilt angle of the second wafer.

公开(公告)号：US12178035B2

公开(公告)日：2024-12-24

申请号：US17824010

申请日：2022-05-25

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chin-Te Kuo

IPC: H10B12/00 ,  H01L29/66 ,  H01L29/786

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a dielectric layer, a first metallization layer, a first channel layer, a second metallization layer, and a second channel layer. The dielectric layer is disposed on the substrate. The first metallization layer is disposed within the dielectric layer and extends along a first direction. The first channel layer is surrounded by the first metallization layer. The second metallization layer is disposed within the dielectric layer and extends along the first direction. The second channel layer is surrounded by the second metallization layer. The first metallization layer includes a first protruding portion protruding toward the second metallization layer.

公开(公告)号：US12176051B2

公开(公告)日：2024-12-24

申请号：US18193645

申请日：2023-03-31

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yi-Hsuan Chu

IPC: G11C29/00 ,  G11C29/12 ,  G11C29/36 ,  G11C29/46

Abstract: A test method is for testing a decision feedback equalization (DFE) of a memory device is provided. The memory device includes a memory bank. The test method includes: providing a first test data pattern having a first data transition frequency and a second test data pattern having a second data transition frequency different from the first data transition frequency; writing the first test data pattern into a first memory section of the memory bank with a first DFE; writing the second test data pattern into a second memory section of the memory bank with the first DFE; reading a first reading data pattern stored in the first memory section and a second reading data pattern stored in the second memory section; and generating a test result signal according to the first reading data pattern and the second reading data pattern.

公开(公告)号：US12175652B2

公开(公告)日：2024-12-24

申请号：US17678200

申请日：2022-02-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ken-Huan Ho

IPC: G06T7/00 ,  G06T7/33 ,  G06T7/60

Abstract: A system, method, and non-transitory computer-readable medium for identifying a cause of manufacturing defects are provided. The system includes a processing unit and an image capture unit electrically coupled to the processing unit. The system is configured to capture, by the image capture unit, a number N of images covering different portions of a semiconductor wafer, wherein each of the number N of images comprises a number M of geometric features. The system is further configured to specify a number M of serial numbers, each associated with one of the number M of geometric features. The system is further configured to calculate, by the processing unit, a geometric center for each of the geometric features of the number N of images. The system is further configured to calculate, based on the number N of images, a number M of average geometric centers associated with the number M of serial numbers. The system is further configured to calculate a shift amount for each geometric feature of the number N of images.

公开(公告)号：US20240413005A1

公开(公告)日：2024-12-12

申请号：US18208142

申请日：2023-06-09

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jen-I LAI

IPC: H01L21/762 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3115

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes: providing a semiconductor structure, in which the semiconductor structure comprises a silicon substrate having a plurality of trenches and an oxide material filled in the trenches and covering the silicon substrate, and the trenches define a plurality of island structures; forming a pad oxide layer on a top portion of the oxide material, in which the pad oxide layer is located over the silicon substrate; and removing the pad oxide layer, so that a top surface of the oxide material and a top surface of the island structures are coplanar.

公开(公告)号：US20240413004A1

公开(公告)日：2024-12-12

申请号：US18207591

申请日：2023-06-08

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yu Jie JIANG ,  Tseng-Fu LU ,  Jhen-Yu TSAI

IPC: H01L21/762 ,  H01L21/324 ,  H01L21/8238 ,  H01L29/08

Abstract: A semiconductor device manufacturing method includes the following steps. A well implant process is performed on a region of a substrate. A source/drain implant process is performed on the region of the substrate. An active area is defined on the region of the substrate. Shallow trench isolations are formed in the active area. An annealing process is performed to the region of the substrate.

公开(公告)号：US20240407155A1

公开(公告)日：2024-12-05

申请号：US18203820

申请日：2023-05-31

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Kuo Chung HSU ,  En-Jui LI

IPC: H10B12/00

Abstract: A semiconductor memory device includes a substrate, a memory cell contact formed over the substrate, a bit line conductive structure formed over the substrate and a dielectric spacer located between the memory cell contact and the bit line conductive structure. The dielectric spacer includes an air gap having a rectangular cross-section, and the rectangular cross-section has a height H and a width W, wherein a H/W ratio is equal to or greater than 40.

公开(公告)号：US12159852B2

公开(公告)日：2024-12-03

申请号：US17730342

申请日：2022-04-27

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Sheng-Hui Yang

IPC: H01L23/00

Abstract: A semiconductor device structure includes a silicon layer disposed over a first semiconductor die, and a first mask layer disposed over the silicon layer. The semiconductor device structure also includes a second semiconductor die disposed over the first mask layer, and a through silicon via penetrating through the silicon layer and the first mask layer. A bottom surface of the through silicon via is greater than a top surface of the through silicon via, and the top surface of the through silicon via is greater than a cross-section of the through silicon via between and parallel to the top surface and the bottom surface of the through silicon via.

公开(公告)号：US12159831B2

公开(公告)日：2024-12-03

申请号：US18508581

申请日：2023-11-14

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Tzu-Ching Tsai

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L23/532 ,  H01L25/00 ,  H01L25/065

Abstract: A circuit device includes: a first substrate having a first barrier layer; a second substrate having a second barrier layer; a first conductive portion arranged over the first barrier layer; a second conductive portion arranged over the second barrier layer; a first expanding pad arranged on the first conductive portion and including a first contact area greater than that of the first conductive portion; and a second expanding pad bonded to the first expanding pad, arranged on the second conductive portion and including a second expanded contact area greater than that of the second conductive portion. The first barrier layer and the second barrier layer include aluminum fluoride.