公开(公告)号：US08748989B2

公开(公告)日：2014-06-10

申请号：US13407507

申请日：2012-02-28

Applicant: Yu Chao Lin ,  Chih-Tang Peng ,  Shun-Hui Yang ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen

Inventor： Yu Chao Lin ,  Chih-Tang Peng ,  Shun-Hui Yang ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen

IPC: H01L21/70

CPC classification number: H01L21/3065 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924

Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a major surface; a plurality of first trenches having a first width and extending downward from the substrate major surface to a first height, wherein a first space between adjacent first trenches defines a first fin; and a plurality of second trenches having a second width less than first width and extending downward from the substrate major surface to a second height greater than the first height, wherein a second space between adjacent second trenches defines a second fin.

Abstract translation: 本发明涉及鳍状场效应晶体管（FinFET）。 FinFET的示例性结构包括：包括主表面的衬底; 多个第一沟槽，具有第一宽度并从所述衬底主表面向下延伸到第一高度，其中相邻第一沟槽之间的第一空间限定第一鳍片; 以及多个第二沟槽，其具有小于第一宽度的第二宽度并且从所述衬底主表面向下延伸到大于所述第一高度的第二高度，其中相邻第二沟槽之间的第二空间限定第二鳍片。

公开(公告)号：US08735252B2

公开(公告)日：2014-05-27

申请号：US13490635

申请日：2012-06-07

Applicant: Weibo Yu ,  Ming-Hsi Yeh ,  Chih-Tang Peng ,  Hao-Ming Lien ,  Chao-Cheng Chen ,  Syun-Ming Jang

Inventor： Weibo Yu ,  Ming-Hsi Yeh ,  Chih-Tang Peng ,  Hao-Ming Lien ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC: H01L21/336

CPC classification number: H01L21/76224 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor IC is disclosed. The method includes receiving a device. The device includes a semiconductor substrate, a plurality of fins and trenches between fins in the semiconductor substrate. The method also includes filling the trenches with a dielectric material to form shallow trench isolations (STI), applying a low-thermal-budget annealing to the dielectric material, and applying a wet-treatment to the dielectric material.

Abstract translation: 公开了制造半导体IC的方法。 该方法包括接收设备。 该器件包括半导体衬底，半导体衬底中的翅片之间的多个散热片和沟槽。 该方法还包括用介电材料填充沟槽以形成浅沟槽隔离（STI），对介电材料施加低热预算退火，以及对电介质材料进行湿法处理。

公开(公告)号：US20130309834A1

公开(公告)日：2013-11-21

申请号：US13471649

申请日：2012-05-15

Applicant: Tzu-Yen Hsieh ,  Ming-Ching Chang ,  Yuan-Sheng Huang ,  Ming-Chia Tai ,  Chao-Cheng Chen

Inventor： Tzu-Yen Hsieh ,  Ming-Ching Chang ,  Yuan-Sheng Huang ,  Ming-Chia Tai ,  Chao-Cheng Chen

IPC: H01L21/283 ,  H01L21/02

CPC classification number: H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device, patterning a first hard mask to form a first recess in a high-resistor (Hi-R) stack, removing the first hard mask, forming a second recess in the Hi-R stack, forming a second hard mask in the second recess in the Hi-R stack. A HR can then be formed in the semiconductor substrate by the second hard mask and a gate trench etch.

Abstract translation: 公开了制造半导体集成电路（IC）的方法。 该方法包括接收半导体器件，图案化第一硬掩模以在高电阻（Hi-R）堆叠中形成第一凹槽，去除第一硬掩模，在Hi-R堆叠中形成第二凹槽，形成第二 硬掩模在Hi-R堆叠的第二个凹槽中。 然后可以通过第二硬掩模和栅沟​​槽蚀刻在半导体衬底中形成HR。

公开(公告)号：US08409964B2

公开(公告)日：2013-04-02

申请号：US13399488

申请日：2012-02-17

Applicant: Jhon-Jhy Liaw ,  Chao-Cheng Chen ,  Chia-Wei Chang

Inventor： Jhon-Jhy Liaw ,  Chao-Cheng Chen ,  Chia-Wei Chang

IPC: H01L21/76

CPC classification number: H01L21/823878 ,  H01L21/76232

Abstract: A shallow trench isolation (STI) structure and methods of forming a STI structure are disclosed. An embodiment is a method for forming a semiconductor structure. The method includes forming a recess in a semiconductor substrate; forming a first material on sidewalls of the recess; forming a widened recessed portion through a bottom surface of the recess; removing the first material from the sidewalls of the recess; and forming a dielectric material in the recess and the widened recessed portion. The bottom surface of the recess is exposed through the first material, and the bottom surface of the recess has a first width. The widened recessed portion has a second width. The second width is greater than the first width.

Abstract translation: 公开了浅沟槽隔离（STI）结构和形成STI结构的方法。 实施例是形成半导体结构的方法。 该方法包括在半导体衬底中形成凹陷; 在所述凹部的侧壁上形成第一材料; 通过所述凹部的底面形成加宽的凹部; 从所述凹部的侧壁去除所述第一材料; 以及在所述凹部和所述加宽的凹部中形成介电材料。 凹部的底面通过第一材料露出，凹部的底面具有第一宽度。 加宽的凹部具有第二宽度。 第二宽度大于第一宽度。

公开(公告)号：US08273632B2

公开(公告)日：2012-09-25

申请号：US13281862

申请日：2011-10-26

Applicant: Yu Chao Lin ,  Ming-Ching Chang ,  Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen

Inventor： Yu Chao Lin ,  Ming-Ching Chang ,  Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen

IPC: H01L21/336

CPC classification number: H01L21/32139 ,  H01L21/0276 ,  H01L21/28194 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/823437 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over the first layer. The second layer is substantially thinner than the first layer. The method includes patterning the second layer with a photoresist material through a first etching process to form a patterned second layer. The method includes patterning the first layer with the patterned second layer through a second etching process to form a patterned first layer. The first and second layers have substantially different etching rates during the second etching process. The method includes patterning the patternable layer with the patterned first layer through a third etching process.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括在衬底上形成可图案化层。 该方法包括在可图案层上形成第一层。 该方法包括在第一层上形成第二层。 第二层比第一层薄得多。 该方法包括通过第一蚀刻工艺用光致抗蚀剂材料图案化第二层以形成图案化的第二层。 该方法包括通过第二蚀刻工艺将具有图案化的第二层的第一层图案化以形成图案化的第一层。 第一和第二层在第二蚀刻工艺期间具有显着不同的蚀刻速率。 该方法包括通过第三蚀刻工艺对具有图案化的第一层的图案化层进行图案化。

公开(公告)号：US08120094B2

公开(公告)日：2012-02-21

申请号：US11838666

申请日：2007-08-14

Applicant: Jhon-Jhy Liaw ,  Chao-Cheng Chen ,  Chia-Wei Chang

Inventor： Jhon-Jhy Liaw ,  Chao-Cheng Chen ,  Chia-Wei Chang

IPC: H01L29/94 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119 ,  H01L31/113

CPC classification number: H01L21/823878 ,  H01L21/76232

Abstract: A shallow trench isolation (STI) structure has a top portion tapering in width from wide to narrow in a direction from a substrate surface, from a first width at a top of the first portion to a second width at a bottom of the first portion. The STI structure also includes a bottom portion below the top portion, which expands from the bottom of the top portion to a substantially widened lateral distance having a third width. The third width is, in general, substantially larger than the second width. The inventive STI structure can provide desired isolation characteristics with a significantly reduced aspect ratio, thus suitable for device isolations in advanced processing technology.

Abstract translation: 浅沟槽隔离（STI）结构具有在从基板表面的方向上从宽到窄的宽度从第一部分的顶部处的第一宽度到第一部分的底部处的第二宽度的顶部部分。 STI结构还包括在顶部下方的底部，其从顶部的底部膨胀到具有第三宽度的基本上加宽的横向距离。 通常，第三宽度基本上大于第二宽度。 本发明的STI结构可以提供期望的隔离特性，具有显着减小的纵横比，因此适用于先进加工技术中的器件隔离。

公开(公告)号：US08053323B1

公开(公告)日：2011-11-08

申请号：US12938571

申请日：2010-11-03

Applicant: Yu Chao Lin ,  Ming-Ching Chang ,  Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen

Inventor： Yu Chao Lin ,  Ming-Ching Chang ,  Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen

IPC: H01L21/336

CPC classification number: H01L21/32139 ,  H01L21/0276 ,  H01L21/28194 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/823437 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over the first layer. The second layer is substantially thinner than the first layer. The method includes patterning the second layer with a photoresist material through a first etching process to form a patterned second layer. The method includes patterning the first layer with the patterned second layer through a second etching process to form a patterned first layer. The first and second layers have substantially different etching rates during the second etching process. The method includes patterning the patternable layer with the patterned first layer through a third etching process.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括在衬底上形成可图案化层。 该方法包括在可图案层上形成第一层。 该方法包括在第一层上形成第二层。 第二层比第一层薄得多。 该方法包括通过第一蚀刻工艺用光致抗蚀剂材料图案化第二层以形成图案化的第二层。 该方法包括通过第二蚀刻工艺将具有图案化的第二层的第一层图案化以形成图案化的第一层。 第一和第二层在第二蚀刻工艺期间具有显着不同的蚀刻速率。 该方法包括通过第三蚀刻工艺对具有图案化的第一层的图案化层进行图案化。

公开(公告)号：US20060151430A1

公开(公告)日：2006-07-13

申请号：US11358393

申请日：2006-02-21

Applicant: Hui Yang ,  Miao-Ju Hsu ,  Chao-Cheng Chen ,  Hun-Jan Tao

Inventor： Hui Yang ,  Miao-Ju Hsu ,  Chao-Cheng Chen ,  Hun-Jan Tao

IPC: G01L21/30 ,  G01R31/00

CPC classification number: H01L21/31116 ,  H01J37/32935 ,  H01L22/26

Abstract: A method of processing multi-layer films, the method including: (1) processing a plurality of layers according to selected parameters, (2) determining a plurality of optical characteristics each associated with one of the plurality of layers and determined during the processing of the associated one of the plurality of layers, and (3) determining dynamic processing progressions each based on one of the plurality of optical characteristics that is associated with a particular one of the plurality of layers undergoing the processing.

Abstract translation: 一种处理多层薄膜的方法，该方法包括：（1）根据选定的参数处理多个层，（2）确定多个光学特性，每个光学特性与多个层之一相关联，并在处理过程中确定 所述多个层中的相关联的一个层，以及（3）基于与经历所述处理的所述多个层中的特定一个层相关联的所述多个光学特性中的一个来确定动态处理进度。

公开(公告)号：US07067433B2

公开(公告)日：2006-06-27

申请号：US10706382

申请日：2003-11-12

Applicant: Wen-Jui Fu ,  Shang-Ru Shen ,  Yun-Hung Shen ,  Chao-Cheng Chen

Inventor： Wen-Jui Fu ,  Shang-Ru Shen ,  Yun-Hung Shen ,  Chao-Cheng Chen

IPC: H01L21/00

CPC classification number: H01L21/31116 ,  H01L21/02046

Abstract: A method of reducing fluorine contamination on a integrated circuit wafer surface is achieved. The method comprises placing an integrated circuit wafer on a cathode stage. The integrated circuit wafer comprises a surface contaminated with fluorine. The integrated circuit wafer is plasma treated with a plasma comprising a reducing gas that forms HF from the fluorine and a bombardment gas that removes the fluorine from the surface. The cathode stage is heated to thereby increase the rate of the fluorine removal.

Abstract translation: 实现了降低集成电路晶片表面上的氟污染的方法。 该方法包括将集成电路晶片放置在阴极级上。 集成电路晶片包括被氟污染的表面。 集成电路晶片用包括从氟形成HF的还原气体的等离子体等离子体处理，以及从表面除去氟的轰击气体。 加热阴极级，从而提高除氟率。

公开(公告)号：US07022610B2

公开(公告)日：2006-04-04

申请号：US10743979

申请日：2003-12-22

Applicant: Chun-Li Chou ,  Yih-Ann Lin ,  Yi-Chen Huang ,  Chao-Cheng Chen ,  Hun-Jan Tao

Inventor： Chun-Li Chou ,  Yih-Ann Lin ,  Yi-Chen Huang ,  Chao-Cheng Chen ,  Hun-Jan Tao

IPC: H01L21/302

CPC classification number: H01L21/02071 ,  H01L21/02063 ,  H01L21/76807

Abstract: A method for cleaning semiconductor substrates includes a DI water clean operation that uses a spin speed no greater than 350 rpm. The cleaning method may include additional cleaning operations such as an organic clean, an aqueous chemical clean or a DI water/ozone clean. The cleaning method may be used to clean substrates after the conclusion of an etching procedure which exposes a single film between a Cu-containing conductive material and the environment. The spin speed of the DI water clean operation prevents copper corrosion due to breakdown of the film that separates the Cu-containing conductive material from the environment.

Abstract translation: 用于清洁半导体衬底的方法包括使用不大于350rpm的旋转速度的去离子水清洁操作。 清洁方法可以包括附加的清洁操作，例如有机清洁剂，水性化学清洁剂或去离子水/臭氧清洁剂。 在完成了在含Cu导电材料和环境之间暴露单个膜的蚀刻过程结束之前，清洁方法可用于清洁衬底。 去离子水清洁操作的旋转速度可防止由于将含Cu导电材料与环境分离的膜破裂导致铜腐蚀。