中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

69 records (took 0.023 seconds)

    NANOSHEET FIELD-EFFECT TRANSISTORS FORMED WITH SACRIFICIAL SPACERS
    61.
    发明申请
    NANOSHEET FIELD-EFFECT TRANSISTORS FORMED WITH SACRIFICIAL SPACERS 审中-公开

    公开(公告)号：US20200066894A1

    公开(公告)日：2020-02-27

    申请号：US16106291

    申请日：2018-08-21

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Julien Frougier ,  Ruilong Xie ,  Daniel Chanemougame

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768

    Abstract: Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A layer stack includes nanosheet channel layers arranged to alternate with sacrificial layers. First and second gate structures are formed that extend across the layer stack and that are separated by a first gap. First and sidewall spacers are formed over the layer stack and within the first gap respectively adjacent to the first and second gate structures, and the layer stack is subsequently etched to form first and second body features that are separated by a second gap. The sacrificial layers are recessed relative to the nanosheet channel layers to define indents in the first and second body features, and the first and second sidewall spacers are subsequently removed. After removing the first and second sidewall spacers, a conformal layer is deposited in the second gap that fills the indents to define inner spacers.

    Method to form low resistance contact
    63.
    发明授权
    Method to form low resistance contact 有权

    公开(公告)号：US10374040B1

    公开(公告)日：2019-08-06

    申请号：US16005832

    申请日：2018-06-12

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Daniel Chanemougame ,  Lars Liebmann ,  Ruilong Xie

    IPC: H01L29/08 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/06 ,  H01L21/768 ,  H01L23/528 ,  H01L27/088

    Abstract: In the manufacture of a semiconductor device, electrical interconnects are formed by depositing a dielectric layer over source/drain regions, and forming a continuous trench within the dielectric layer. The trench may traverse plural source/drain regions associated with adjacent devices. The electrical interconnects are thereafter formed by metallizing the trench and patterning the metallization layers to form discrete interconnects over and in electrical contact with respective source/drain regions. The source/drain interconnects exhibit a reentrant profile, which presents a larger contact area to later-formed conductive contacts than a conventional tapered profile, and thus improve manufacturability and yield.

    VERTICAL-TRANSPORT TRANSISTORS WITH SELF-ALIGNED CONTACTS
    65.
    发明申请
    VERTICAL-TRANSPORT TRANSISTORS WITH SELF-ALIGNED CONTACTS 审中-公开

    公开(公告)号：US20190051757A1

    公开(公告)日：2019-02-14

    申请号：US15671605

    申请日：2017-08-08

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Emilie Bourjot ,  Daniel Chanemougame ,  Tek Po Rinus Lee ,  Ruilong Xie ,  Hui Zang

    IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423

    Abstract: Methods and structures that include a vertical-transport field-effect transistor. A semiconductor fin is formed that projects from a first source/drain region. A second source/drain region is spaced vertically along the semiconductor fin from the first source/drain region. A gate stack is arranged between the second source/drain region and the first source/drain region. A spacer is formed adjacent to a sidewall of the second source/drain region. A first contact is connected with a top surface of the second source/drain region, a second contact is connected with a top surface of the first source/drain region, and a third contact is connected with a top surface of the gate stack. The spacer is arranged between the second source/drain region and the second contact or between the second source/drain region and the third contact.

    METHODS OF FORMING A GATE CONTACT STRUCTURE ABOVE AN ACTIVE REGION OF A TRANSISTOR
    66.
    发明申请
    METHODS OF FORMING A GATE CONTACT STRUCTURE ABOVE AN ACTIVE REGION OF A TRANSISTOR 审中-公开

    公开(公告)号：US20180315822A1

    公开(公告)日：2018-11-01

    申请号：US15581105

    申请日：2017-04-28

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Hao Tang ,  Cheng Chi ,  Daniel Chanemougame ,  Lars W. Liebmann ,  Mark V. Raymond

    IPC: H01L29/417 ,  H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  H01L23/535 ,  H01L29/78 ,  H01L29/45

    Abstract: One method includes forming a gate above a semiconductor substrate, the gate comprising a gate structure and a gate cap positioned above the gate structure, forming a conductive source/drain metallization structure adjacent the gate in each of the source/drain regions and forming a recess in each of the conductive source/drain metallization structures. The method further includes forming a spacer structure that comprises recess filling portions that substantially fill the recesses and a portion that extends across the gate cap, wherein a portion of the gate cap is exposed within the spacer structure, forming an insulating material within the spacer structure and on the exposed portion of the gate cap, forming a gate contact opening that exposes a portion of an upper surface of the gate structure and forming a conductive gate contact structure (CB) in the conductive gate contact opening.

Patent Agency Ranking