公开(公告)号：US11749577B2

公开(公告)日：2023-09-05

申请号：US18089536

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Ravindranath Mahajan ,  Digvijay Raorane

IPC: H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/367 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49568 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/16 ,  H01L24/20 ,  H01L24/24 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/02371

Abstract: A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

公开(公告)号：US11735552B2

公开(公告)日：2023-08-22

申请号：US16451754

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Sergio Antonio Chan Arguedas ,  Jimin Yao ,  Chandra Mohan Jha

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/367

CPC classification number: H01L24/17 ,  H01L23/16 ,  H01L23/3675 ,  H01L23/562 ,  H01L2224/1713 ,  H01L2224/17051 ,  H01L2224/17163 ,  H01L2224/17181 ,  H01L2224/17519

Abstract: Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.

公开(公告)号：US11735533B2

公开(公告)日：2023-08-22

申请号：US16437254

申请日：2019-06-11

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Ravindranath Mahajan ,  Robert Sankman ,  Shawna Liff ,  Srinivas Pietambaram ,  Bharat Penmecha

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/3511

Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

公开(公告)号：US11581235B2

公开(公告)日：2023-02-14

申请号：US17234671

申请日：2021-04-19

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Ravindranath Mahajan ,  Digvijay Raorane

IPC: H01L23/34 ,  H01L21/00 ,  H01L23/367 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/495

Abstract: A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

公开(公告)号：US11430724B2

公开(公告)日：2022-08-30

申请号：US16646529

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Robert L. Sankman ,  Robert Nickerson ,  Mitul Modi ,  Sanka Ganesan ,  Rajasekaran Swaminathan ,  Omkar Karhade ,  Shawna M. Liff ,  Amruthavalli Alur ,  Sri Chaitra J. Chavali

IPC: H01L23/52 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

公开(公告)号：US11387175B2

公开(公告)日：2022-07-12

申请号：US16059535

申请日：2018-08-09

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Sanka Ganesan ,  Pilin Liu ,  Shawna Liff ,  Sri Chaitra Chavali ,  Sandeep Gaan ,  Jimin Yao ,  Aastha Uppal

IPC: H01L23/28 ,  H01L23/34 ,  H01L23/538 ,  H01L23/532 ,  H01L23/498

Abstract: Embodiments include an electronics package and methods of forming such packages. In an embodiment, the electronics package comprises a first package substrate. In an embodiment, the first package substrate comprises, a die embedded in a mold layer, a thermal interface pad over a surface of the die, and a plurality of solder balls over the thermal interface pad. In an embodiment, the thermal interface pad and the solder balls are electrically isolated from circuitry of the electronics package. In an embodiment, the electronics package further comprises a second package substrate over the first package substrate.

公开(公告)号：US11328968B2

公开(公告)日：2022-05-10

申请号：US16463638

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Mitul Modi ,  Robert L. Sankman ,  Debendra Mallik ,  Ravindranath V. Mahajan ,  Amruthavalli P. Alur ,  Yikang Deng ,  Eric J. Li

IPC: H01L23/13 ,  H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00

Abstract: An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.

公开(公告)号：US11328937B2

公开(公告)日：2022-05-10

申请号：US16915290

申请日：2020-06-29

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Debendra Mallik ,  Bassam M. Ziadeh ,  Yoshihiro Tomita

IPC: H01L21/00 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L23/16

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

公开(公告)号：US20210366862A1

公开(公告)日：2021-11-25

申请号：US17392598

申请日：2021-08-03

Applicant: Intel Corporation

Inventor： Zhaozhi Li ,  Sanka Ganesan ,  Debendra Mallik ,  Gregory Perry ,  Kuan H. Lu ,  Omkar Karhade ,  Shawna M. Liff

IPC: H01L23/00

Abstract: An electronic package and method includes a substrate including a plurality of pads on a major surface. An electronic component including a plurality of pads on a major surface facing the major surface of the substrate. A stud bump electrically couples one of the plurality of pads of the substrate to one of the plurality of pads of the electronic component.

公开(公告)号：US11164818B2

公开(公告)日：2021-11-02

申请号：US16363698

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Tarek Ibrahim ,  Kristof Darmawikarta ,  Rahul N. Manepalli ,  Debendra Mallik ,  Robert L. Sankman

IPC: H01L23/538 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.