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公开(公告)号:US20220215261A1
公开(公告)日:2022-07-07
申请号:US17706256
申请日:2022-03-28
Applicant: Micron Technology, Inc.
Inventor: Aswin Thiruvengadam , Daniel L. Lowrance , Joshua Phelps , Peter B. Harrington
Abstract: Disclosed is a system comprising a memory component having a plurality of memory cells capable of being in a plurality of states, each state of the plurality of states corresponding to a value stored by the memory cell, and a processing device, operatively coupled with the memory component, to perform operations comprising: obtaining, for the plurality of memory cells, a plurality of distributions of threshold voltages, wherein each of the plurality of distributions corresponds to one of the plurality of states, classifying each of the plurality of distributions among one of a plurality of classes, generating a vector comprising a plurality of components, wherein each of the plurality of components represents the class of a respective one of the plurality of distributions, and processing, using a classifier, the generated vector to determine a likelihood that the memory component will fail within a target period of time.
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公开(公告)号:US11226896B2
公开(公告)日:2022-01-18
申请号:US17007117
申请日:2020-08-31
Applicant: Micron Technology, Inc.
Inventor: Aswin Thiruvengadam , Daniel L. Lowrance , Peter Feeley
IPC: G06F12/02 , G11C11/406 , G11C16/20 , G11C16/34 , G06F13/16 , G11C16/32 , G06F16/18 , G11C7/20 , G11C29/02 , G11C29/44
Abstract: The present disclosure includes apparatuses and methods related to determining trim settings on a memory device. An example apparatus can determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells.
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公开(公告)号:US20210391319A1
公开(公告)日:2021-12-16
申请号:US17459589
申请日:2021-08-27
Applicant: Micron Technology, Inc.
Inventor: Daniel G. Scobee , Aleksandr Semenuk , Aswin Thiruvengadam
Abstract: A thermal chamber includes a cavity that is enclosed by sides and one or more ports that expose the cavity within the thermal chamber. Each of the one or more ports is configured to receive a temperature control component having a solid physical structure and configured to transfer thermal energy to and from an electrical device exposed via the cavity. The thermal chamber includes a bottom side open area of the thermal chamber located below the one or more ports. The bottom side open area is configured to allow the temperature control component to contact the electrical device that is exposed via the bottom side open area.
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公开(公告)号:US11101015B2
公开(公告)日:2021-08-24
申请号:US16222295
申请日:2018-12-17
Applicant: Micron Technology, Inc.
Inventor: Aswin Thiruvengadam , Sivagnanam Parthasarathy , Preston Thomson
IPC: G11C29/38 , G11C29/36 , G06F11/263
Abstract: A target vector representing a usage parameter corresponding to a test of a memory component is generated. A test sample is assigned to the target vector and a set of path variables are generated for the test sample. A test process of the test is executed using the test sample in accordance with the set of path variables to generate a test result. A failure associated with the test result is identified.
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公开(公告)号:US11036631B2
公开(公告)日:2021-06-15
申请号:US15802551
申请日:2017-11-03
Applicant: Micron Technology, Inc.
Inventor: Aswin Thiruvengadam , Daniel L. Lowrance , Peter Feeley
IPC: G06F12/02 , G11C16/20 , G11C16/32 , G11C11/406 , G11C16/34 , G06F13/16 , G06F16/18 , G11C7/20 , G11C29/26 , G11C29/02 , G11C29/04
Abstract: The present disclosure includes apparatuses and methods related to configurable trim settings on a memory device. An example apparatus can include configuring a set of trim settings for an array of memory cells such that the array of memory cells have desired operational characteristics in response to being operated with the set of trim settings.
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公开(公告)号:US10777292B2
公开(公告)日:2020-09-15
申请号:US16587283
申请日:2019-09-30
Applicant: Micron Technology, Inc.
Inventor: Aswin Thiruvengadam , Daniel L. Lowrance , Peter Feeley
IPC: G11C8/00 , G11C29/02 , G11C16/10 , G06F12/02 , G11C16/32 , G06F3/06 , G11C7/10 , G06F16/18 , G11C16/34 , G11C7/04 , G11C29/44
Abstract: The present disclosure includes apparatuses and methods related to selectable trim settings on a memory device. An example apparatus can store a number of sets of trim settings and select a particular set of trims settings of the number of sets of trim settings based on desired operational characteristics for the array of memory cells.
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公开(公告)号:US10761980B2
公开(公告)日:2020-09-01
申请号:US16442792
申请日:2019-06-17
Applicant: Micron Technology, Inc.
Inventor: Aswin Thiruvengadam , Daniel L. Lowrance , Peter Feeley
IPC: G11C11/40 , G06F12/02 , G11C11/406 , G11C16/20 , G11C16/34 , G06F13/16 , G11C16/32 , G06F16/18 , G11C7/20 , G11C29/02 , G11C29/44
Abstract: The present disclosure includes apparatuses and methods related to determining trim settings on a memory device. An example apparatus can determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells.
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公开(公告)号:US10535415B2
公开(公告)日:2020-01-14
申请号:US15802597
申请日:2017-11-03
Applicant: Micron Technology, Inc.
Inventor: Aswin Thiruvengadam , Daniel L. Lowrance , Peter Feeley
Abstract: Apparatuses and methods related to a memory system including a controller and an array of memory cells are provided. An apparatus can include a controller configured to receive operational characteristics of an array of memory cells based on prior operations performed by the array of memory cells, determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells, and send the set of trim settings to the array of memory cells.
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公开(公告)号:US20190138442A1
公开(公告)日:2019-05-09
申请号:US15802551
申请日:2017-11-03
Applicant: Micron Technology, Inc.
Inventor: Aswin Thiruvengadam , Daniel L. Lowrance , Peter Feeley
Abstract: The present disclosure includes apparatuses and methods related to configurable trim settings on a memory device. An example apparatus can include configuring a set of trim settings for an array of memory cells such that the array of memory cells have desired operational characteristics in response to being operated with the set of trim settings.
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公开(公告)号:US09454427B2
公开(公告)日:2016-09-27
申请号:US14855203
申请日:2015-09-15
Applicant: MICRON TECHNOLOGY, INC.
Inventor: Aswin Thiruvengadam , Angelo Visconti , Mauro Bonanomi , Richard E. Fackenthal , William Melton
IPC: G11C29/00 , G06F11/10 , G06F11/16 , G06F11/07 , G06F3/06 , G11C7/10 , G11C13/00 , G11C16/10 , G11C19/00
CPC classification number: G06F11/1008 , G06F3/0619 , G06F3/064 , G06F3/0644 , G06F3/0673 , G06F3/0679 , G06F11/0751 , G06F11/1048 , G06F11/1666 , G11C7/1006 , G11C7/1012 , G11C13/0004 , G11C13/0069 , G11C16/10 , G11C19/00
Abstract: This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error.
Abstract translation: 本公开涉及通过将要编程的数据移动到存储器以避免硬错误而避免在写入时间期间的存储器中的硬错误。 在一个实现中,将数据编程到存储器阵列的方法包括获得与所选择的存储器单元相对应的错误数据,移位数据模式,使得所选存储器单元要存储的值与硬错误相关联的值匹配,以及 将移位的数据模式编程到存储器阵列,使得编程到所选择的存储器单元的值与与硬错误相关联的值匹配。
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