公开(公告)号：US20210295917A1

公开(公告)日：2021-09-23

申请号：US17342116

申请日：2021-06-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gary L. Howe ,  Scott E. Smith

IPC: G11C16/08 ,  G11C7/06 ,  G11C8/10

Abstract: Apparatuses and methods for decoding addresses for memory are disclosed. An example apparatus includes a memory cell array and a row decoder. The memory cell array includes a bank of memory including a plurality of groups of memory. Each of the groups of memory includes sections of memory, and each of the sections of memory including memory cells arranged in rows and columns of memory. The row decoder decodes addresses to access a first group of memory to include rows of prime memory from a first block of memory and to include rows of prime memory from a second block of memory. The row decoder decodes the addresses to access a second group of memory to include rows of prime memory from the second block of memory and to include rows of redundant memory. The rows of redundant memory are shared with the first and second blocks of memory.

公开(公告)号：US10929283B2

公开(公告)日：2021-02-23

申请号：US16543810

申请日：2019-08-19

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe

IPC: G06F12/02 ,  G06F12/0855 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises a cache coupled to an array of memory cells and a controller. The controller is configured to perform a first operation beginning at a first address to transfer data from the array of memory cells to the cache, and perform a second operation concurrently with the first operation, the second operation beginning at a second address.

公开(公告)号：US20210011803A1

公开(公告)日：2021-01-14

申请号：US17038251

申请日：2020-09-30

Applicant: Micron Technology, Inc.

Inventor： Gary L. Howe

IPC: G06F11/10 ,  G11C11/4063 ,  G11C11/4076

Abstract: A semiconductor device may include a memory bank and a plurality of mode registers that communicatively couple to each of the plurality of memory banks. The plurality of mode registers may include a pattern of data stored therein. The semiconductor device may also include a bank control that receives a write pattern command that causes the bank control to write the pattern of data into the memory bank, send a signal to a multiplexer to couple the plurality of mode registers to the memory bank, and write the pattern of data to the memory bank via the plurality of mode registers.

公开(公告)号：US20200227118A1

公开(公告)日：2020-07-16

申请号：US16249714

申请日：2019-01-16

Applicant: Micron Technology, Inc.

Inventor： Gary L. Howe ,  Scott E. Smith

IPC: G11C16/08 ,  G11C8/10 ,  G11C7/06

Abstract: Apparatuses and methods for decoding addresses for memory are disclosed. An example apparatus includes a memory cell array and a row decoder. The memory cell array includes a bank of memory including a plurality of groups of memory. Each of the groups of memory includes sections of memory, and each of the sections of memory including memory cells arranged in rows and columns of memory. The row decoder decodes addresses to access a first group of memory to include rows of prime memory from a first block of memory and to include rows of prime memory from a second block of memory. The row decoder decodes the addresses to access a second group of memory to include rows of prime memory from the second block of memory and to include rows of redundant memory. The rows of redundant memory are shared with the first and second blocks of memory.

公开(公告)号：US10608621B2

公开(公告)日：2020-03-31

申请号：US16050978

申请日：2018-07-31

Applicant: Micron Technology, Inc.

Inventor： Gary L. Howe ,  Jeffrey E. Koelling

IPC: H03K5/15 ,  H03K5/156 ,  G11C7/22 ,  H03K5/159

Abstract: The present disclosure relates generally to improved systems and methods for control of one or more timing signals in a memory device. More specifically, the present disclosure relates to configurable duty cycle correction at one or more DQ pins (e.g., data input/output (I/O) pins) of the memory device. For example, the memory device may include a configurable phase splitter and/or selective capacitive loading circuitry implemented to adjust the duty cycle of a timing signal at one or more DQ pins during and/or after manufacture of the memory device. Accordingly, the memory device may include increased flexibility and granularity of control over the one or more timing signals.

公开(公告)号：US10402116B2

公开(公告)日：2019-09-03

申请号：US15837685

申请日：2017-12-11

Applicant: Micron Technology, Inc.

Inventor： Byung S. Moon ,  Harish N. Venkata ,  Gary L. Howe ,  Myung Ho Bae

IPC: G06F3/06 ,  G11C11/4072 ,  G11C29/52 ,  G06F11/10

Abstract: A memory device may include a memory array that includes multiple memory cells. The memory device may also include multiple sense amplifiers that, in operation, may each be connected to one or more memory cells. The sense amplifiers may be designed to assist in writing logical zeros to the multiple memory cells.

公开(公告)号：US10387046B2

公开(公告)日：2019-08-20

申请号：US15189900

申请日：2016-06-22

Applicant: Micron Technology, Inc.

Inventor： Thanh K. Mai ,  Gary L. Howe ,  Daniel B. Penney

IPC: G11C8/00 ,  G06F3/06 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.

公开(公告)号：US20190146869A1

公开(公告)日：2019-05-16

申请号：US15812949

申请日：2017-11-14

Applicant: Micron Technology, Inc.

Inventor： Gary L. Howe

IPC: G06F11/10 ,  G11C11/4063 ,  G11C29/52

Abstract: A semiconductor device may include a memory bank and a plurality of mode registers that communicatively couple to each of the plurality of memory banks. The plurality of mode registers may include a pattern of data stored therein. The semiconductor device may also include a bank control that receives a write pattern command that causes the bank control to write the pattern of data into the memory bank, send a signal to a multiplexer to couple the plurality of mode registers to the memory bank, and write the pattern of data to the memory bank via the plurality of mode registers.

公开(公告)号：US20190066790A1

公开(公告)日：2019-02-28

申请号：US16110992

申请日：2018-08-23

Applicant: Micron Technology, Inc.

Inventor： Thanh K. Mai ,  Gary L. Howe

IPC: G11C16/08 ,  G11C11/16 ,  G11C11/406

CPC classification number: G11C16/08 ,  G11C5/063 ,  G11C7/1045 ,  G11C11/161 ,  G11C11/40603 ,  G11C11/4076 ,  G11C11/408 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008

Abstract: A semiconductor device may include a plurality of memory banks, a plurality of mode registers that may control an operational mode associated with each of the plurality of memory banks, and a set of global wiring lines coupled to each of the plurality of mode registers. The set of global wiring lines may include a first global wiring line to transmit data to each of the plurality of mode registers, a second global wiring line to transmit an address signal to each of the plurality of mode registers, a third global wiring line to transmit a read command signal to each of the plurality of mode registers, and a fourth global wiring line to transmit a write command signal to each of the plurality of mode registers.

公开(公告)号：US20180024926A1

公开(公告)日：2018-01-25

申请号：US15214982

申请日：2016-07-20

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe

IPC: G06F12/0815

CPC classification number: G06F12/0215 ,  G06F12/0859 ,  G06F13/16 ,  G06F2212/1016 ,  G06F2212/1028 ,  Y02D10/13

Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises a cache coupled to an array of memory cells and a controller. The controller is configured to perform a first operation beginning at a first address to transfer data from the array of memory cells to the cache, and perform a second operation concurrently with the first operation, the second operation beginning at a second address.