公开(公告)号：US20230315623A1

公开(公告)日：2023-10-05

申请号：US18206958

申请日：2023-06-07

Applicant: Micron Technology, Inc.

Inventor： Zhengang Chen ,  Jianmin Huang

IPC: G06F12/02 ,  G06F12/14 ,  G06F13/16 ,  H04L9/06 ,  H04L9/08 ,  G11C11/56

CPC classification number: G06F12/0246 ,  G06F12/1408 ,  G06F13/1668 ,  H04L9/0662 ,  H04L9/0869 ,  G11C11/5628 ,  G06F2212/7207

Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums that provide for techniques for scrambling and/or updating meta-data that enable an efficient internal copyback operation. In some examples, improved data distribution techniques decouple the scrambling key from a physical address to allow for copyback operations while maintaining data distribution requirements across a memory device. The controller may generate a seed value that is used by a scrambling algorithm to scramble the host-data and meta-data prior to the data being written. The seed value is then encoded and written to the page with encoded versions of the scrambled user data and meta-data—the random seed is written without scrambling the random seed.

公开(公告)号：US11776655B2

公开(公告)日：2023-10-03

申请号：US17965481

申请日：2022-10-13

Applicant: Micron Technology, Inc.

Inventor： Sri Rama Namala ,  Jung Sheng Hoei ,  Jianmin Huang ,  Ashutosh Malshe ,  Xiangang Luo

IPC: G11C29/18 ,  G11C29/44 ,  G11C29/40

CPC classification number: G11C29/4401 ,  G11C29/18 ,  G11C29/40 ,  G11C2029/1806 ,  G11C2029/4002

Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).

公开(公告)号：US11749346B2

公开(公告)日：2023-09-05

申请号：US17324538

申请日：2021-05-19

Applicant: Micron Technology, Inc.

Inventor： Tomoko Ogura Iwasaki ,  Kulachet Tanpairoj ,  Jianmin Huang ,  Lawrence Celso Miranda ,  Sheyang Ning

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C11/56

CPC classification number: G11C16/10 ,  G11C16/3459 ,  G11C11/56 ,  G11C16/0483

Abstract: Described are systems and methods for performing memory programming operations in the overwrite mode. An example memory device includes: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: responsive to identifying a first data item to be stored by a portion of the memory array, causing a first memory programming operation to be performed to program, to a first target threshold voltage, a set of memory cells included by the portion of the memory array; and responsive to identifying a second data item to be stored by the portion of the memory array, causing a second memory programming operation to be performed to program the set of memory cells to a second target threshold voltage exceeding the first target threshold voltage.

公开(公告)号：US20230185479A1

公开(公告)日：2023-06-15

申请号：US18105043

申请日：2023-02-02

Applicant: Micron Technology, Inc.

Inventor： Tao Liu ,  Ting Luo ,  Jianmin Huang

IPC: G06F3/06 ,  G11C16/34

CPC classification number: G06F3/0655 ,  G06F3/0679 ,  G06F3/0604 ,  G11C16/349

Abstract: A method includes determining a first memory access count threshold for a first word line of a block of memory cells and determining a second memory access count threshold for a second word line of the block of memory cells. The second memory access count threshold can be greater than the first memory access count threshold. The method can further include incrementing a memory block access count corresponding to the block of memory cells that includes the first word line and the second word line in response to receiving a memory access command and refreshing the first word line when the memory block access count corresponding to the block of memory cells is equal to the first memory access count threshold.

公开(公告)号：US11675411B2

公开(公告)日：2023-06-13

申请号：US17470506

申请日：2021-09-09

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Xiangang Luo ,  Ting Luo ,  Jianmin Huang

IPC: G06F1/3206 ,  G06F12/06 ,  G06F12/02 ,  G06F1/3296

CPC classification number: G06F1/3206 ,  G06F1/3296 ,  G06F12/0246 ,  G06F12/06

Abstract: Systems and methods are disclosed, including, in a storage system comprising control circuitry and a memory array having multiple groups of memory cells, storing a first physical-to-logical (P2L) data structure for a first physical area of a first group of memory cells in a second physical area of the first group of memory cells, such as when resuming operation from a low-power state, including an asynchronous power loss (APL). The first group of memory cells can include a super block of memory cells. A second P2L data structure for the second physical area of the first group of memory cells can be stored, such as in a metadata area of the second physical area and an address of the first P2L data structure can be stored in the second P2L data structure.

公开(公告)号：US11625176B2

公开(公告)日：2023-04-11

申请号：US17870320

申请日：2022-07-21

Applicant: Micron Technology, Inc.

Inventor： Carla L. Christensen ,  Jianmin Huang ,  Sebastien Andre Jean ,  Kulachet Tanpairoj

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/0893

Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The configuration (e.g., the size and position) of the SLC cache may have an impact on power consumption, speed, and other performance of the memory device. An operating system of an electronic device to which the memory device is installed may wish to achieve different performance of the device based upon certain conditions detectable by the operating system. In this way, the performance of the memory device can be customized by the operating system through adjustments of the performance characteristics of the SLC cache.

公开(公告)号：US11599416B1

公开(公告)日：2023-03-07

申请号：US17464290

申请日：2021-09-01

Applicant: Micron Technology, Inc.

Inventor： Jianmin Huang ,  Xiangang Luo ,  Kulachet Tanpairoj

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07 ,  G06F3/06

Abstract: An apparatus includes a media management superblock component. The media management superblock component determines that a quantity of blocks of a superblock of a non-volatile memory array are bad blocks. The media management superblock component compares the quantity of bad blocks to a bad block criteria. The media management superblock component writes host data to the superblock with the quantity of bad blocks in response to the quantity of bad blocks meeting the bad block criteria.

公开(公告)号：US20230069159A1

公开(公告)日：2023-03-02

申请号：US17464290

申请日：2021-09-01

Applicant: Micron Technology, Inc.

Inventor： Jianmin Huang ,  Xiangang Luo ,  Kulachet Tanpairoj

IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06

Abstract: An apparatus includes a media management superblock component. The media management superblock component determines that a quantity of blocks of a superblock of a non-volatile memory array are bad blocks. The media management superblock component compares the quantity of bad blocks to a bad block criteria. The media management superblock component writes host data to the superblock with the quantity of bad blocks in response to the quantity of bad blocks meeting the bad block criteria.

公开(公告)号：US20230061800A1

公开(公告)日：2023-03-02

申请号：US17464316

申请日：2021-09-01

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Jianmin Huang ,  Xiangang Luo

IPC: G06F3/06

Abstract: A method includes forming at least a portion of a first superblock using a first subset of blocks from at least one memory die of a memory sub-system and forming at least a portion of a second superblock using a second subset of blocks from the at least one memory die of the memory sub-system.

公开(公告)号：US20220413699A1

公开(公告)日：2022-12-29

申请号：US17362542

申请日：2021-06-29

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Ashutosh Malshe ,  Huachen Li ,  Giuseppe D'eliseo ,  Jianmin Huang

IPC: G06F3/06

Abstract: An apparatus can include a partial superblock memory management component. The partial superblock memory management component can identify bad blocks in respective planes of a block of non-volatile memory cells. The partial superblock memory management component can determine that a plane of the respective planes includes at least good block in at least one different block of non-volatile memory cells. The partial superblock memory management component can perform an operation to reallocate the at least one good block in the plane to the at least one bad block in the plane to form blocks of non-volatile memory cells having a quantity of bad blocks that satisfies a bad block threshold.