公开(公告)号：US20140160851A1

公开(公告)日：2014-06-12

申请号：US13707067

申请日：2012-12-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

IPC: G11C16/06

CPC classification number: G11C16/3459 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2213/71

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

Abstract translation: 一些实施例包括具有存储单元串的装置和方法，所述存储单元串包括位于装置的不同级别中的存储器单元和耦合到存储单元串的数据线。 存储单元串包括与存储单元相关联的柱体。 这种装置中的至少一个可以包括被配置为在存储器单元之间存储信息到存储器单元中的模块和/或确定存储器单元中存储在存储单元中的信息的值。 该模块还可以被配置为向数据线和/或源施加具有正值的电压以控制身体的电位。 描述其他实施例。

公开(公告)号：US20250118653A1

公开(公告)日：2025-04-10

申请号：US18981288

申请日：2024-12-13

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Roger W. Lindsay ,  Krishna K. Parat

IPC: H01L23/52 ,  G11C13/00 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B63/00 ,  H10N70/00

Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The features extend horizontally though a primary portion of the stack with at least some of the features extending extend farther in the horizontal direction in an end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the openings. Other aspects and implementations are disclosed.

公开(公告)号：US20220189552A1

公开(公告)日：2022-06-16

申请号：US17561656

申请日：2021-12-23

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Shafqat Ahmed ,  Khaled Hasnat ,  Krishna K. Parat

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/26 ,  G11C16/34 ,  G11C16/12 ,  G11C16/14 ,  G11C16/06

Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

公开(公告)号：US11211126B2

公开(公告)日：2021-12-28

申请号：US17027425

申请日：2020-09-21

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Shafqat Ahmed ,  Khaled Hasnat ,  Krishna K. Parat

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/26 ,  G11C16/34 ,  G11C16/12 ,  G11C16/14 ,  G11C16/06 ,  G11C16/10

Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

公开(公告)号：US20200243437A1

公开(公告)日：2020-07-30

申请号：US16850692

申请日：2020-04-16

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Roger W. Lindsay ,  Krishna K. Parat

IPC: H01L23/52 ,  H01L27/10 ,  G11C13/00 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/24 ,  H01L45/00 ,  H01L27/1157

Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the horizontally elongated openings. Other aspects and implementations are disclosed.

公开(公告)号：US20200051904A1

公开(公告)日：2020-02-13

申请号：US16654908

申请日：2019-10-16

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Roger W. Lindsay ,  Krishna K. Parat

IPC: H01L23/52 ,  H01L27/10 ,  G11C13/00 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/24 ,  H01L45/00 ,  H01L27/1157

Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the horizontally elongated openings. Other aspects and implementations are disclosed.

公开(公告)号：US10475515B2

公开(公告)日：2019-11-12

申请号：US15850708

申请日：2017-12-21

Applicant: Micron Technology, Inc.

Inventor： Benben Li ,  Akira Goda ,  Ramey M. Abdelrahaman ,  Ian C. Laboriante ,  Krishna K. Parat

IPC: G11C16/04 ,  H01L27/11524 ,  H01L45/00 ,  H01L27/24 ,  H01L27/11597 ,  H01L27/11558 ,  G11C11/408 ,  G11C8/08

Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

公开(公告)号：US20190147966A1

公开(公告)日：2019-05-16

申请号：US16228733

申请日：2018-12-20

Applicant: Micron Technology, Inc.

Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

IPC: G11C16/34 ,  G11C16/06 ,  G11C16/16 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  G11C16/32

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

公开(公告)号：US10217799B2

公开(公告)日：2019-02-26

申请号：US15686389

申请日：2017-08-25

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L27/24 ,  H01L27/1158 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11553 ,  H01L45/00

Abstract: Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.

公开(公告)号：US20180350827A1

公开(公告)日：2018-12-06

申请号：US15980503

申请日：2018-05-15

Applicant: Micron Technology, Inc.

Inventor： Charles H. Dennison ,  Akira Goda ,  John Hopkins ,  Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L27/11556 ,  H01L29/66 ,  H01L27/11578 ,  H01L21/28

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L27/11578 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.