公开(公告)号：US20130124831A1

公开(公告)日：2013-05-16

申请号：US13730842

申请日：2012-12-29

Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benney Eitan

Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benney Eitan

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

公开(公告)号：US20130124364A1

公开(公告)日：2013-05-16

申请号：US13325291

申请日：2011-12-14

Applicant: Millind Mittal

Inventor： Millind Mittal

IPC: G06Q30/06

CPC classification number: G06Q30/06 ,  G06Q20/385

Abstract: A computerized method of payment based on short, temporary, transaction ID numbers which protect the security of the payer's (customer's) financial accounts. The payee will first register a source of funds and a payer device with a unique ID (such as a mobile phone and phone number) with the invention's payment server. Then once a payee (merchant) and the payer have agreed on a financial transaction amount, the payee requests a transaction ID from the payment server for that amount. The payment server sends the payee a transaction ID, which the payee then communicates to the payer. The payer in turn relays this transaction ID to the server, which validates the transaction using the payer device. The server then releases funds to the payee. The server can preserve all records for auditing purposes, but security is enhanced because the merchant never gets direct access to the customer's financial account information.

Abstract translation: 基于短暂，临时，交易ID号码的计算机化付款方式，保护付款人（客户）的财务账户的安全。 收款人将首先使用发明的付款服务器注册资金来源和具有唯一ID（如手机和电话号码）的付款人设备。 然后一旦收款人（商家）和付款人已经同意了金融交易金额，收款人就从付款服务器请求该金额的交易ID。 付款服务器向收款人发送交易ID，收款人然后与付款人进行通信。 付款人又将此交易ID中继到服务器，该服务器使用付款人设备验证交易。 服务器然后向收款人发放资金。 服务器可以保留所有记录以进行审计，但是由于商家无法直接访问客户的财务帐户信息，因此安全性得到增强。

公开(公告)号：US20130091190A1

公开(公告)日：2013-04-11

申请号：US13633086

申请日：2012-10-01

Applicant: Alexander Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Carole Dulong ,  Eiichi Kowashi ,  Wolf C. Witt

Inventor： Alexander Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Carole Dulong ,  Eiichi Kowashi ,  Wolf C. Witt

IPC: G06F7/60

CPC classification number: G06F7/60 ,  G06F7/4812 ,  G06F7/49921 ,  G06F7/5324 ,  G06F7/5338 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30112 ,  G06F15/7817 ,  G06F17/10 ,  G06F17/147 ,  G06F17/16 ,  G06F2207/3828 ,  G06T1/20

Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

公开(公告)号：US20110131402A1

公开(公告)日：2011-06-02

申请号：US12977459

申请日：2010-12-23

Applicant: Millind Mittal

Inventor： Millind Mittal

IPC: G06F15/177

CPC classification number: G06F21/72 ,  G06F12/1408 ,  G06F12/1441 ,  G06F12/1491 ,  G06F21/60 ,  G06F21/602 ,  G06F21/78 ,  G06F2221/2107 ,  G06F2221/2125

Abstract: A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

公开(公告)号：US07596634B2

公开(公告)日：2009-09-29

申请号：US10352800

申请日：2003-01-27

Applicant: Millind Mittal ,  Murali Repakula

Inventor： Millind Mittal ,  Murali Repakula

IPC: G06F15/16

CPC classification number: H04L29/06 ,  H04L69/10 ,  H04L69/16 ,  H04L69/161 ,  H04L69/165

Abstract: Offloading application level communication functions from a host processor. The offloading apparatus can be configured as either a pre-processor or as a co-processor. An interface is provided for receiving a network message sent to the host. An engine performs processing of the network message above OSI level 4. In one embodiment, in a fast-path, a response to the message is sent back to the network without any involvement by the host, providing a complete offload. For other messages, certain pre-processing can be performed, such as parsing of a header, message authentication, and look-up of meta-data. The results of the look-up are then passed to the host with the processed header, simplifying the tasks the host needs to perform. The messages and data are transferred to the host using control and data buffers.

Abstract translation: 从主机处理器卸载应用程序级通信功能。 卸载装置可以被配置为预处理器或协处理器。 提供了一个用于接收发送到主机的网络消息的接口。 引擎执行OSI级别4之上的网络消息的处理。在一个实施例中，在快速路径中，对消息的响应被发送回网络而不需要主机的任何参与，从而提供完整的卸载。 对于其他消息，可以执行某些预处理，例如分析报头，消息认证和元数据查找。 然后将查找结果传递给具有处理头的主机，从而简化了主机执行的任务。 消息和数据使用控制和数据缓冲区传输到主机。

公开(公告)号：US07461109B2

公开(公告)日：2008-12-02

申请号：US11758767

申请日：2007-06-06

Applicant: Derrick Chu Lin ,  Punit Minocha ,  Alexander D. Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

Inventor： Derrick Chu Lin ,  Punit Minocha ,  Alexander D. Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

IPC: G06F5/01

CPC classification number: G06F7/762 ,  G06F5/01 ,  G06F7/49994 ,  G06F7/76 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3885

Abstract: A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. One embodiment of a central processing unit (CPU) includes instruction fetch logic to fetch a single-instruction-multiple-data (SIMD) shift instruction. A register stores a multiple data elements to be operated upon by the SIMD shift instruction. A barrel shifter concurrently shifts the data elements in a bit-wise manner by a variable number of bit positions in response to the SIMD shift instruction.

Abstract translation: 一种用于在处理器中提供对具有多个值的压缩数据元素进行移位操作的方法和装置。 中央处理单元（CPU）的一个实施例包括提取单指令多数据（SIMD）移位指令的指令提取逻辑。 寄存器存储通过SIMD移位指令来操作的多个数据元素。 桶形移位器响应于SIMD移位指令，同时将数据元素按比特方式移位可变数目的位位置。

公开(公告)号：US07430560B1

公开(公告)日：2008-09-30

申请号：US11309160

申请日：2006-07-03

Applicant: Millind Mittal

Inventor： Millind Mittal

IPC: G06F7/00

CPC classification number: G06F17/30961 ,  Y10S707/99942 ,  Y10S707/99943

Abstract: A lookup is performed using multiple levels of compressed stride tables in a multi-bit Trie structure. An input lookup key is divided into several strides including a current stride of S bits. A valid entry in a current stride table is located by compressing the S bits to form a compressed index of D bits into the current stride table. A compression function logically combines the S bits to generate the D compressed index bits. An entry in a prior-level table points to the current stride table and has a field indicating which compression function and mask to use. Compression functions can include XOR, shifts, rotates, and multi-bit averaging. Rather than store all 2S entries, the current stride table is compressed to store only 2D entries. Ideally, the number of valid entries in the current stride table is between 2D−1 and 2D for maximum compression. Storage requirements are reduced.

Abstract translation: 在多位Trie结构中使用多级压缩步幅表进行查找。 输入查找键被分成包括S位的当前步幅的几个步骤。 通过压缩S位来形成当前步幅表中的有效条目，以形成D位的压缩索引到当前步幅表中。 压缩函数逻辑组合S位以产生D压缩索引位。 前一级表中的条目指向当前步幅表，并具有指示要使用的压缩函数和掩码的字段。 压缩功能可以包括XOR，移位，旋转和多位平均。 而不是存储所有2个SUPER条目，当前步幅被压缩以仅存储2个条目。 理想情况下，当前步幅表中的有效条目的数目在最大压缩之间的2个D-1和2个D / D之间。 存储要求降低。

公开(公告)号：US07191318B2

公开(公告)日：2007-03-13

申请号：US10249416

申请日：2003-04-07

Applicant: Tarun Kumar Tripathy ,  Millind Mittal ,  Kaushik L. Popat ,  Amod Bodas

Inventor： Tarun Kumar Tripathy ,  Millind Mittal ,  Kaushik L. Popat ,  Amod Bodas

IPC: G06F9/00

CPC classification number: H04L29/06 ,  H04L69/10 ,  H04L69/16 ,  H04L69/161 ,  H04L69/165

Abstract: A copy instruction executed by a functional-level instruction-set computing (FLIC) processor copies a variable-length data block from one resource to another resource through a cross-bar switch. Resources include general-purpose registers, input, output, and execution buffers, DRAM, SRAM, and other memory. A copy-with-validate instruction has an operand pointing to a first rule in an immediate rule table. The first rule controls validation of a first data-item in the data being copied. Validation includes range and equality checking of the data-item. The value of the data-item or the current offset can be written to a register. A format field in the rule indicates the size of the data-item, or the size is read from the data-item for variable-size formats. The current offset is incremented by the size. The next data-item is validated by a next rule, and other rules in the immediate table control validation of other data-items in the data block.

Abstract translation: 由功能级指令集计算（FLIC）处理器执行的复制指令通过交叉开关将可变长度数据块从一个资源复制到另一个资源。 资源包括通用寄存器，输入，输出和执行缓冲器，DRAM，SRAM和其他存储器。 具有验证复制指令的操作数指向立即规则表中的第一条规则。 第一个规则控制要复制的数据中第一个数据项的验证。 验证包括数据项的范围和等式检查。 可以将数据项或当前偏移量的值写入寄存器。 规则中的格式字段指示数据项的大小，或从可变大小格式的数据项中读取大小。 当前的偏移量增加大小。 下一个数据项由下一个规则验证，立即表中的其他规则控制数据块中其他数据项的验证。

公开(公告)号：US20070028019A1

公开(公告)日：2007-02-01

申请号：US11230242

申请日：2005-09-19

Applicant: Millind Mittal

Inventor： Millind Mittal

IPC: G06F13/38 ,  G06F13/12

CPC classification number: G06F3/0233 ,  H04M2250/70

Abstract: Systems and methods are disclosed for entering data into a keypad having a plurality of keys, each key used to select one character from at least first, second and third characters designated for each key. The method includes providing disambiguation information on a current key and subsequently selecting a next key covering a desired character. In another aspect, for the keyboards where touching and key, and subsequent untouching or pressing a key are taken as two separate events. In this case the disambiguation information is provided by key touched immediately prior to the key pressed or untouched. In yet another method where the touching of a key when there was no prior touched key (first-touch key), and touching a new key without untouching the keypad are taken as two separate events, the first-touch key is taken as a selection of key with one of the desired characters, and a subsequent touching of an adjacent key without untouching of the keypad is used to index and select the characters on the selected key.

Abstract translation: 公开了用于将数据输入到具有多个键的键盘中的系统和方法，每个键用于从为每个键指定的至少第一，第二和第三字符中选择一个字符。 该方法包括提供关于当前密钥的消歧信息，随后选择覆盖期望字符的下一个密钥。 在另一方面，对于触摸和键的键盘以及随后的不触摸或按键被视为两个单独的事件。 在这种情况下，消歧信息是通过紧接按键或未触摸之前立即触摸的键来提供的。 在另一种方法中，当没有先前触摸的键（第一触摸键）时触摸一个键，并且触摸一个新的键而不触摸键盘则被视为两个单独的事件，将第一触摸键作为选择 使用所需字符之一的键，并且随后触摸相邻的键而不用触摸小键盘来索引并选择所选择的键上的字符。

公开(公告)号：US07149882B2

公开(公告)日：2006-12-12

申请号：US10844606

申请日：2004-05-11

Applicant: Andrew F. Glew ,  Larry M. Mennemeier ,  Alexander D. Peleg ,  David Bistry ,  Millind Mittal ,  Carole Dulong ,  Eiichi Kowashi ,  Benny Eitan ,  Derrik Lin ,  Romamohan R. Vakkalagadda

Inventor： Andrew F. Glew ,  Larry M. Mennemeier ,  Alexander D. Peleg ,  David Bistry ,  Millind Mittal ,  Carole Dulong ,  Eiichi Kowashi ,  Benny Eitan ,  Derrik Lin ,  Romamohan R. Vakkalagadda

IPC: G06F7/38

CPC classification number: G06F9/3017 ,  G06F9/30036 ,  G06F9/30105 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30134 ,  G06F9/30189 ,  G06F9/384 ,  G06F9/462

Abstract: A processor with instructions to operate on different data types stored in a single logical register file. According to one embodiment of the invention, a processor includes a number of physical registers, a memory unit, and a decode/execution unit. The memory unit is to make the number of physical registers appear to software as a single software-visible register file. The decode/execution unit is to execute on the contents of the single software-visible register file instructions of a first instruction type and of a second instruction type, wherein the single software-visible register file is to be operated as a flat register file during execution of instructions of the second instruction type and as a stack referenced register file during execution of instructions of the first instruction type.

Abstract translation: 具有对存储在单个逻辑寄存器文件中的不同数据类型进行操作的指令的处理器。 根据本发明的一个实施例，处理器包括多个物理寄存器，存储器单元和解码/执行单元。 存储单元是将物理寄存器的数量作为单个软件可见的寄存器文件显示在软件上。 解码/执行单元执行第一指令类型和第二指令类型的单个软件可见寄存器文件指令的内容，其中单个软件可见寄存器文件将作为平坦寄存器文件操作 在执行第一指令类型的指令期间执行第二指令类型的指令和作为堆栈引用的寄存器堆栈。