公开(公告)号：US20210202437A1

公开(公告)日：2021-07-01

申请号：US16952084

申请日：2020-11-19

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498

Abstract: A package structure including a redistribution circuit structure, an insulator, a plurality of conductive connection pieces, a first chip, a second chip, an encapsulant, a third chip, and a plurality of conductive terminals is provided. The redistribution circuit structure has first and second connection surfaces opposite to each other. The insulator is embedded in and penetrates the redistribution circuit structure. The conductive connection pieces penetrate the insulator. The first and second chips are disposed on the first connection surface. The encapsulant is disposed on the redistribution circuit structure and at least laterally covers the first and second chips. The third chip is disposed on the second connection surface and electrically connected to the first and second chips through the conductive connection pieces. The conductive terminals are disposed on the second connection surface and electrically connected to the first chip or the second chip through the redistribution circuit structure.

公开(公告)号：US20210202363A1

公开(公告)日：2021-07-01

申请号：US16952044

申请日：2020-11-18

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/053 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: The disclosure provides a package structure including a redistribution circuit structure, a first circuit board, a second circuit board, a first insulator, multiple conductive terminals, and a package. The redistribution circuit structure has a first connection surface and a second connection surface opposite to each other. The first circuit board and the second circuit board are disposed on the first connection surface and are connected electrically to the redistribution circuit structure. The first insulator is disposed on the first connection surface and covers the first circuit board and the second circuit board. The conductive terminals are connected electrically to and disposed on the first circuit board or the second circuit board. The package is disposed on the second connection surface and is connected electrically to the redistribution circuit structure. A manufacturing method of a package structure is also provided.

公开(公告)号：US20210098324A1

公开(公告)日：2021-04-01

申请号：US16583286

申请日：2019-09-26

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Hung-Hsin Hsu ,  Wen-Hsiung Chang

IPC: H01L23/31 ,  H01L27/146 ,  H01L21/768

Abstract: By using a photosensitive material coating or laminating on the substrate, an opening well structure with plurality of openings and pillars is formed by photolithography or mechanical processing to have patterns corresponding to the active sensor areas of the chip die so as to provide improved support on the substrate for the cover glass. The overall package structure is then reinforced without the risk of cracking the substrate.

公开(公告)号：US10862202B1

公开(公告)日：2020-12-08

申请号：US16524197

申请日：2019-07-29

Applicant: Powertech Technology Inc.

Inventor： Yun-Hsin Yeh ,  Hung-Hsin Hsu

IPC: H01Q1/38 ,  H01Q21/00 ,  H01Q23/00

Abstract: An integrated antenna package structure including a circuit board, a chip, an encapsulant and an antenna is provided. The chip is disposed on the circuit board and electrically connected to the circuit board. The encapsulant encapsulates the chip. The antenna is embedded in the encapsulant. The antenna has a first outer surface, the encapsulant has a second outer surface, and the first outer surface is substantially coplanar with the second outer surface. A manufacturing method of an integrated antenna package structure is also provided.

公开(公告)号：US20200328161A1

公开(公告)日：2020-10-15

申请号：US16830235

申请日：2020-03-25

Applicant: Powertech Technology Inc.

Inventor： Nan-Chun Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien

IPC: H01L23/538 ,  H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A chip package structure including a first chip, an encapsulant, a first redistribution layer, a second redistribution layer, a second chip, and a third chip is provided. The first chip has an active surface, a back side surface opposite to the active surface, a plurality of conductive vias, and a plurality of conductive connectors disposed on the back side surface. The encapsulant covers the active surface, the back side surface, and the conductive connectors. The encapsulant has a first encapsulating surface and a second encapsulating surface opposite to the first encapsulating surface. The first redistribution layer is disposed on the first encapsulating surface. The second redistribution layer is disposed on the second encapsulating surface. The second chip is disposed on the second redistribution layer. The third chip is disposed on the second redistribution layer. A manufacturing method of a chip package structure is also provided.

公开(公告)号：US20200006290A1

公开(公告)日：2020-01-02

申请号：US16019551

申请日：2018-06-27

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

Abstract: A package structure including first and second packages is provided. The first package includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, and a plurality of conductive wire segments. The semiconductor die has an active surface and a back surface. The insulating encapsulant encapsulates the semiconductor die. The first redistribution layer is disposed on the back surface of the semiconductor die and a bottom surface of the insulating encapsulant. The first redistribution layer has a first surface and a second surface opposite to the first surface. The second redistribution layer is disposed on the active surface of the semiconductor die. The plurality of conductive wire segments electrically connects the semiconductor die to the second redistribution layer and the first redistribution layer to the second redistribution layer. The second package is stacked on the second surface of the first redistribution layer over the first package.

公开(公告)号：US20190393200A1

公开(公告)日：2019-12-26

申请号：US16016672

申请日：2018-06-25

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/56

Abstract: A package structure includes a first redistribution structure, a die, a plurality of conductive sheets, a plurality of conductive balls, and a first encapsulant. The first redistribution structure has a first surface and a second surface opposite to the first surface. The die has a plurality of connection pads electrically connected to the first surface of the first redistribution structure. The conductive sheets are electrically connected to the first surface of the first redistribution structure. The conductive balls are correspondingly disposed on the conductive sheets and are electrically coupled to the first surface of the first redistribution structure through the conductive sheets. The first encapsulant encapsulates the die, the conductive sheets, and the conductive balls. The first encapsulant exposes at least a portion of each conductive ball.

公开(公告)号：US10438931B2

公开(公告)日：2019-10-08

申请号：US15871117

申请日：2018-01-15

Applicant: Powertech Technology Inc.

Inventor： Han-Wen Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien ,  Nan-Chun Lin

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L21/78

Abstract: A package structure includes a first redistribution layer, a second redistribution layer, a die, a plurality of conductive pillars and a die-stacked structure. The first redistribution layer has a first surface and a second surface opposite to the first surface. The second redistribution layer is disposed above the first surface. The die is disposed between the first redistribution layer and the second redistribution layer and has an active surface and a rear surface opposite to the active surface. The active surface is adhered to the first surface, and the die is electrically connected to the first redistribution layer. The conductive pillars are disposed and electrically connected between the first redistribution layer and the second redistribution layer. The die-stacked structure is bonded on the second redistribution layer.

公开(公告)号：US20190214367A1

公开(公告)日：2019-07-11

申请号：US15867613

申请日：2018-01-10

Applicant: Powertech Technology Inc.

Inventor： Ming-Chih Chen ,  Hung-Hsin Hsu ,  Yuan-Fu Lan ,  Chi-An Wang ,  Hsien-Wen Hsu ,  Li-Chih Fang

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/28 ,  H01L23/538 ,  H01L23/552

CPC classification number: H01L25/0657 ,  H01L23/28 ,  H01L23/5384 ,  H01L23/552 ,  H01L25/50

Abstract: A stacked package has plurality of chip packages stacked on a base. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on a lateral side of the chip package. The lateral trace is formed through the encapsulant and electrically connects to the cut edges of the chip packages. The base has an interconnect structure to form the electrical connection between the lateral trace and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.

公开(公告)号：US20190080971A1

公开(公告)日：2019-03-14

申请号：US15705250

申请日：2017-09-14

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin Hsu ,  Shang-Yu Chang Chien ,  Nan-Chun Lin

IPC: H01L21/66 ,  G01R31/02 ,  G01R31/28 ,  H01L23/00

CPC classification number: H01L22/32 ,  G01R31/025 ,  G01R31/2853 ,  G01R31/2884 ,  G01R31/2896 ,  H01L22/14 ,  H01L22/34 ,  H01L24/02 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381

Abstract: A testing method of a packaging process includes following steps. A substrate is provided. A circuit structure is formed on the substrate. The circuit structure includes a real unit area and a dummy side rail surrounding the real unit area, and a plurality of first circuit patterns is disposed on the real unit area. A second circuit pattern is formed on the dummy side rail, and the second circuit pattern emulates the configurations of at least a portion of the first circuit patterns for operating a simulation test. In addition, a packaging structure adapted for a testing process is also mentioned.