公开(公告)号：US20130299971A1

公开(公告)日：2013-11-14

申请号：US13937849

申请日：2013-07-09

Applicant: STATS ChipPAC, Ltd.

Inventor： Byung Tai Do ,  Reza A. Pagaila ,  Linda Pei Ee Chua

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3011 ,  H01L2224/19 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a plurality of bumps formed over a carrier. A semiconductor die is mounted to the carrier between the bumps. A penetrable film encapsulant layer having a base layer, first adhesive layer, and second adhesive layer is placed over the semiconductor die and bumps. The penetrable film encapsulant layer is pressed over the semiconductor die and bumps to embed the semiconductor die and bumps within the first and second adhesive layers. The first adhesive layer and second adhesive layer are separated to remove the base layer and first adhesive layer and leave the second adhesive layer around the semiconductor die and bumps. The bumps are exposed from the second adhesive layer. The carrier is removed. An interconnect structure is formed over the semiconductor die and second adhesive layer. A conductive layer is formed over the second adhesive layer electrically connected to the bumps.

Abstract translation: 半导体器件具有形成在载体上的多个凸块。 半导体管芯安装在凸块之间的载体上。 具有基层，第一粘合剂层和第二粘合剂层的可穿透膜包封层被放置在半导体管芯和凸块上。 将可穿透的膜包封层压在半导体管芯和凸起上，以将半导体管芯和凸块嵌入第一和第二粘合剂层内。 分离第一粘合剂层和第二粘合剂层以除去基底层和第一粘合剂层，并且将第二粘合剂层留在半导体管芯和凸起周围。 凸起从第二粘合剂层露出。 载体被移除。 在半导体管芯和第二粘合剂层上形成互连结构。 导电层形成在与凸块电连接的第二粘合剂层上。

公开(公告)号：US08530274B2

公开(公告)日：2013-09-10

申请号：US13706818

申请日：2012-12-06

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila

IPC: H01L21/00

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/34 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device is made by mounting an insulating layer over a temporary substrate. A via is formed through the insulating layer. The via is filled with conductive material. A semiconductor die has a stress sensitive region. A dam is formed around the stress sensitive region. The semiconductor die is mounted to the conductive via. The dam creates a gap adjacent to the stress sensitive region. An encapsulant is deposited over the semiconductor die. The dam blocks the encapsulant from entering the gap. The temporary substrate is removed. A first interconnect structure is formed over the semiconductor die. The gap isolates the stress sensitive region from the first interconnect structure. A shielding layer or heat sink can be formed over the semiconductor die. A second interconnect structure can be formed over the semiconductor die opposite the first interconnect structure.

Abstract translation: 半导体器件通过将绝缘层安装在临时衬底上而制成。 通过绝缘层形成通孔。 通孔填充有导电材料。 半导体管芯具有应力敏感区域。 在压力敏感区域周围形成一个坝。 半导体管芯安装在导电通孔上。 大坝在应力敏感区域附近产生间隙。 密封剂沉积在半导体管芯上。 大坝堵塞密封剂进入间隙。 移除临时衬底。 第一互连结构形成在半导体管芯上。 间隙将应力敏感区域与第一互连结构隔离。 可以在半导体管芯上形成屏蔽层或散热器。 可以在与第一互连结构相对的半导体管芯上形成第二互连结构。

公开(公告)号：US09589910B2

公开(公告)日：2017-03-07

申请号：US13846014

申请日：2013-03-18

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Dioscoro A. Merilo

IPC: H01L23/488 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/495 ,  H01L25/065 ,  H01L25/00 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L23/562 ,  H01L21/4832 ,  H01L21/56 ,  H01L21/561 ,  H01L23/495 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a base substrate with first and second opposing surfaces. A first etch-resistant conductive layer is formed over the first surface of the base substrate. A second etch-resistant conductive layer is formed over the second surface of the base substrate. A first semiconductor die has bumps formed over contact pads on an active surface of the first die. The first die is mounted over a first surface of the first conductive layer. An encapsulant is deposited over the first die and base substrate. A portion of the base substrate is removed to form electrically isolated base leads between opposing portions of the first and second conductive layers. A second semiconductor die is mounted over the encapsulant and a second surface of the first conductive layer between the base leads. A height of the base leads is greater than a thickness of the second die.

Abstract translation: 半导体器件具有带有第一和第二相对表面的基底基板。 在基底基板的第一表面上形成第一耐蚀刻导电层。 第二耐蚀刻导电层形成在基底衬底的第二表面上。 第一半导体管芯具有形成在第一管芯的有效表面上的接触焊盘上的凸起。 第一管芯安装在第一导电层的第一表面上。 密封剂沉积在第一管芯和基底衬底上。 去除基底衬底的一部分以在第一和第二导电层的相对部分之间形成电隔离的底部引线。 第二半导体管芯安装在密封剂上方，第一导电层的第二表面位于基底引线之间。 基部引线的高度大于第二管芯的厚度。

公开(公告)号：US09449932B2

公开(公告)日：2016-09-20

申请号：US13886556

申请日：2013-05-03

Applicant: STATS ChipPAC, Ltd.

Inventor： Byung Tai Do ,  Arnel Trasporto ,  Linda Pei Ee Chua ,  Reza A. Pagaila

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48

CPC classification number: H01L24/14 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10175 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/8114 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/381 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2224/13099 ,  H01L2924/0665 ,  H01L2224/05099 ,  H01L2924/00 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A semiconductor device has a base substrate with recesses formed in a first surface of the base substrate. A first conductive layer is formed over the first surface and into the recesses. A second conductive layer is formed over a second surface of the base substrate. A first semiconductor die is mounted to the base substrate with bumps partially disposed within the recesses over the first conductive layer. A second semiconductor die is mounted to the first semiconductor die. Bond wires are formed between the second semiconductor die and the first conductive layer over the first surface of the base substrate. An encapsulant is deposited over the first and second semiconductor die and base substrate. A portion of the base substrate is removed from the second surface between the second conductive layer down to the recesses to form electrically isolated base leads for the bumps and bond wires.

公开(公告)号：US09443829B2

公开(公告)日：2016-09-13

申请号：US14728182

申请日：2015-06-02

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L21/56 ,  H01L21/683 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/11 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/81 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06548 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/81805

Abstract: A semiconductor device has a first interconnect structure. A first semiconductor die has an active surface oriented towards and mounted to a first surface of the first interconnect structure. A first encapsulant is deposited over the first interconnect structure and first semiconductor die. A second semiconductor die has an active surface oriented towards and mounted to a second surface of the first interconnect structure opposite the first surface. A plurality of first conductive pillars is formed over the second surface of the first interconnect structure and around the second semiconductor die. A second encapsulant is deposited over the second semiconductor die and around the plurality of first conductive pillars. A second interconnect structure including a conductive layer and bumps are formed over the second encapsulant and electrically connect to the plurality of first conductive pillars and the first and second semiconductor die.

公开(公告)号：US09443828B2

公开(公告)日：2016-09-13

申请号：US14694811

申请日：2015-04-23

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/36 ,  H01L23/367 ,  H01L23/538 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor device has a first thermally conductive layer formed over a first surface of a semiconductor die. A second surface of the semiconductor die is mounted to a sacrificial carrier. An encapsulant is deposited over the first thermally conductive layer and sacrificial carrier. The encapsulant is planarized to expose the first thermally conductive layer. A first insulating layer is formed over the second surface of the semiconductor die and a first surface of the encapsulant. A portion of the first insulating layer over the second surface of the semiconductor die is removed. A second thermally conductive layer is formed over the second surface of the semiconductor die within the removed portion of the first insulating layer. An electrically conductive layer is formed within the insulating layer around the second thermally conductive layer. A heat sink can be mounted over the first thermally conductive layer.

公开(公告)号：US09331002B2

公开(公告)日：2016-05-03

申请号：US13944783

申请日：2013-07-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC: H01L21/30 ,  H01L23/48 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/50

CPC classification number: H01L23/481 ,  H01L21/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3157 ,  H01L24/18 ,  H01L24/19 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/02371 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/82039 ,  H01L2224/9222 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is made by providing a first semiconductor wafer having semiconductor die. A gap is made between the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a first through hole via (THV). A conductive lining is conformally deposited in the first THV. A solder material is disposed above the conductive lining of the first THV. A second semiconductor wafer having semiconductor die is disposed over the first wafer. A second THV is formed in a gap between the die of the second wafer. A conductive lining is conformally deposited in the second THV. A solder material is disposed above the second THV. The second THV is aligned to the first THV. The solder material is reflowed to form the conductive vias within the gap. The gap is singulated to separate the semiconductor die.

公开(公告)号：US09142515B2

公开(公告)日：2015-09-22

申请号：US14087653

申请日：2013-11-22

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  DaeSik Choi ,  Jun Mo Koo

IPC: H01L23/552 ,  H01L21/56 ,  H01L21/683 ,  H01L25/065 ,  H01L25/00 ,  H01L23/538 ,  H01L23/34 ,  H01L23/522 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/34 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L24/19 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06102 ,  H01L2224/06181 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/221 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/73207 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. A shielding layer is formed between the first and second semiconductor die. An electrical interconnect, such as conductive pillar, bump, or bond wire, is formed between the first and second semiconductor die. A conductive TSV can be formed through the first and second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and electrical interconnect. A heat sink is formed over the second semiconductor die. An interconnect structure, such as a bump, can be formed over the second semiconductor die. A portion of a backside of the first semiconductor die is removed. A protective layer is formed over exposed surfaces of the first semiconductor die. The protective layer covers the exposed backside and sidewalls of the first semiconductor die.

Abstract translation: 半导体晶片具有多个第一半导体管芯。 第二半导体管芯安装到第一半导体管芯。 在第一和第二半导体管芯之间形成屏蔽层。 在第一和第二半导体管芯之间形成诸如导电柱，凸起或接合线的电互连。 可以通过第一和第二半导体管芯形成导电TSV。 密封剂沉积在第一和第二半导体管芯和电互连上。 在第二半导体管芯上形成散热器。 可以在第二半导体管芯上形成诸如凸块的互连结构。 去除第一半导体管芯的背面的一部分。 在第一半导体管芯的暴露表面上形成保护层。 保护层覆盖第一半导体管芯的暴露的背面和侧壁。

公开(公告)号：US20150262977A1

公开(公告)日：2015-09-17

申请号：US14728182

申请日：2015-06-02

Applicant: STATS CHIPPAC, LTD.

Inventor： Reza A. Pagaila

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/11 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/81 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06548 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/81805

Abstract: A semiconductor device has a first interconnect structure. A first semiconductor die has an active surface oriented towards and mounted to a first surface of the first interconnect structure. A first encapsulant is deposited over the first interconnect structure and first semiconductor die. A second semiconductor die has an active surface oriented towards and mounted to a second surface of the first interconnect structure opposite the first surface. A plurality of first conductive pillars is formed over the second surface of the first interconnect structure and around the second semiconductor die. A second encapsulant is deposited over the second semiconductor die and around the plurality of first conductive pillars. A second interconnect structure including a conductive layer and bumps are formed over the second encapsulant and electrically connect to the plurality of first conductive pillars and the first and second semiconductor die.

Abstract translation: 半导体器件具有第一互连结构。 第一半导体管芯具有朝向并安装到第一互连结构的第一表面的有源表面。 第一密封剂沉积在第一互连结构和第一半导体管芯上。 第二半导体管芯具有朝向并安装到与第一表面相对的第一互连结构的第二表面的有源表面。 多个第一导电柱形成在第一互连结构的第二表面上并且围绕第二半导体管芯。 第二密封剂沉积在第二半导体管芯上并围绕多个第一导电柱。 包括导电层和凸块的第二互连结构形成在第二密封剂上并且电连接到多个第一导电柱和第一和第二半导体管芯。

公开(公告)号：US20150249065A1

公开(公告)日：2015-09-03

申请号：US14710393

申请日：2015-05-12

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81024 ,  H01L2224/81201 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/182 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a first substrate with a plurality of first conductive vias formed partially through the first substrate. A first semiconductor die is mounted over the first substrate and electrically connected to the first conductive vias. A plurality of bumps is formed over the first substrate. A second substrate has a plurality of second conductive vias formed partially through the second substrate. A penetrable encapsulant is deposited over the second substrate. The second substrate is mounted over the first substrate to embed the first semiconductor die and interconnect structure in the penetrable encapsulant. The encapsulant can be injected between the first and second substrates. A portion of the first substrate is removed to expose the first conductive vias. A portion of the second substrate is removed to expose the second conductive vias. A second semiconductor die is mounted over the second substrate.

Abstract translation: 半导体器件具有第一衬底，其具有部分地穿过第一衬底形成的多个第一导电通孔。 第一半导体管芯安装在第一衬底上并电连接到第一导电通孔。 在第一基板上形成多个凸块。 第二衬底具有部分地穿过第二衬底形成的多个第二导电通孔。 可渗透的密封剂沉积在第二基底上。 将第二衬底安装在第一衬底上以将第一半导体管芯和互连结构嵌入可渗透的密封剂中。 密封剂可以注射在第一和第二基底之间。 去除第一衬底的一部分以露出第一导电通孔。 去除第二衬底的一部分以暴露第二导电通孔。 第二半导体管芯安装在第二衬底上。