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    Semiconductor device and method of forming microelectromechanical systems (MEMS) package
    61.
    发明授权
    Semiconductor device and method of forming microelectromechanical systems (MEMS) package 有权

    公开(公告)号：US10189702B2

    公开(公告)日：2019-01-29

    申请号：US15362199

    申请日：2016-11-28

    Applicant: STATS ChipPAC Pte. Ltd.

    Inventor： Yaojian Lin ,  Won Kyoung Choi ,  Kang Chen ,  Ivan Micallef

    IPC: B81B7/00 ,  B81C1/00 ,  H01L21/56 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

    Abstract: A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure.

    Semiconductor Device and Method of Forming Embedded Conductive Layer for Power/Ground Planes in FO-EWLB
    64.
    发明申请
    Semiconductor Device and Method of Forming Embedded Conductive Layer for Power/Ground Planes in FO-EWLB 审中-公开

    公开(公告)号：US20170263470A1

    公开(公告)日：2017-09-14

    申请号：US15605010

    申请日：2017-05-25

    Applicant: STATS ChipPAC Pte. Ltd.

    Inventor： Yaojian Lin ,  Xu Sheng Bao ,  Kang Chen

    IPC: H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498

    Abstract: A semiconductor device has a first conductive layer and a semiconductor die disposed adjacent to the first conductive layer. An encapsulant is deposited over the first conductive layer and semiconductor die. An insulating layer is formed over the encapsulant, semiconductor die, and first conductive layer. A second conductive layer is formed over the insulating layer. A first portion of the first conductive layer is electrically connected to VSS and forms a ground plane. A second portion of the first conductive layer is electrically connected to VDD and forms a power plane. The first conductive layer, insulating layer, and second conductive layer constitute a decoupling capacitor. A microstrip line including a trace of the second conductive layer is formed over the insulating layer and first conductive layer. The first conductive layer is provided on an embedded dummy die, interconnect unit, or modular PCB unit.

    System and Method of Providing FOUP or Cassette Supporting Structure for Handling Various Size or Shape Wafers and Panels
    67.
    发明公开
    System and Method of Providing FOUP or Cassette Supporting Structure for Handling Various Size or Shape Wafers and Panels 审中-公开

    公开(公告)号：US20240332051A1

    公开(公告)日：2024-10-03

    申请号：US18193820

    申请日：2023-03-31

    Applicant: STATS ChipPAC Pte. Ltd.

    Inventor： Yaojian Lin ,  DanFeng Yang ,  SongHua Xu

    IPC: H01L21/673

    CPC classification number: H01L21/67383 ,  H01L21/67294

    Abstract: A front opening unified pod has a housing and a plurality of horizontal support members disposed within the housing and adapted to accommodate a plurality of semiconductor wafers or panels. The plurality of semiconductor wafers or panels have a different size or shape, such as circular and rectangular. A first one of the plurality of horizontal support members has a wing to support the plurality of different size or shape semiconductor wafers or panels. The plurality of horizontal support members has a first side horizontal support member, a second side horizontal support member, and a center horizontal support member disposed between the first side horizontal support member and the second side horizontal support member. The plurality of horizontal support members is insertable into the housing. One or more of the plurality of horizontal support members has an opening for laser identification.

    Semiconductor Device and Method of Forming Embedded Wafer Level Chip Scale Packages
    68.
    发明申请
    Semiconductor Device and Method of Forming Embedded Wafer Level Chip Scale Packages 有权

    公开(公告)号：US20230012958A1

    公开(公告)日：2023-01-19

    申请号：US17936714

    申请日：2022-09-29

    Applicant: STATS ChipPAC Pte. Ltd.

    Inventor： Yaojian Lin ,  Pandi C. Marimuthu ,  Il Kwon Shim ,  Byung Joon Han

    IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/786 ,  H01L21/784 ,  H01L21/782 ,  H01L21/82 ,  H01L21/78

    Abstract: A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (μm) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 μm or less.

    Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units
    70.
    发明授权
    Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units 有权

    公开(公告)号：US11024561B2

    公开(公告)日：2021-06-01

    申请号：US16885640

    申请日：2020-05-28

    Applicant: STATS ChipPAC Pte. Ltd.

    Inventor： Il Kwon Shim ,  Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Yu Gu

    IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L23/538

    Abstract: A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package. A total thickness of the semiconductor package and build-up interconnect structure is less than 0.4 millimeters.

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