公开(公告)号：US09633911B2

公开(公告)日：2017-04-25

申请号：US14668482

申请日：2015-03-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc. ,  GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Qing Liu ,  Nicolas Loubet ,  Scott Luning

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L27/22 ,  H01L43/10 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/4966

Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.

公开(公告)号：US20160284607A1

公开(公告)日：2016-09-29

申请号：US14670800

申请日：2015-03-27

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, Inc. ,  STMICROELECTRONICS, INC.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/84 ,  H01L29/78 ,  H01L27/12

CPC classification number: H01L21/845 ,  H01L27/1211 ,  H01L29/7849

Abstract: Fabricating a semiconductor device includes providing a strained semiconductor material (SSM) layer disposed on a dielectric layer, forming a first plurality of fins on the SSOI structure, at least one fin of the first plurality of fins is in a nFET region and at least one fin is in a pFET region, etching portions of the dielectric layer under portions of the SSM layer of the at least one fin in the pFET region, filling areas cleared by the etching, forming a second plurality of fins from the at least one fin in the nFET region such that each fin comprises a portion of the SSM layer disposed on the dielectric layer, and forming a third plurality of fins from the at least one fin in the pFET region such that each fin comprises a portion of the SSM layer disposed on a flowable oxide.

Abstract translation: 制造半导体器件包括提供设置在电介质层上的应变半导体材料（SSM）层，在SSOI结构上形成第一多个鳍片，第一组多个鳍片中的至少一个鳍片在nFET区域中，并且至少一个 鳍状物在pFET区域中，在pFET区域中的至少一个鳍片的SSM层的部分之下蚀刻介电层的部分，通过蚀刻清除的填充区域，从至少一个鳍片形成第二多个鳍片 所述nFET区域使得每个鳍片包括设置在所述电介质层上的所述SSM层的一部分，以及从所述pFET区域中的所述至少一个翅片形成第三多个翅片，使得每个翅片包括设置在所述SSM层上的部分 可流动的氧化物。

公开(公告)号：US20160284602A1

公开(公告)日：2016-09-29

申请号：US14669055

申请日：2015-03-26

Applicant: International Business Machines Corporation ,  Globalfoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/8238 ,  H01L21/306 ,  H01L21/308 ,  H01L21/66 ,  H01L21/768

CPC classification number: H01L21/823871 ,  H01L21/30625 ,  H01L21/3085 ,  H01L21/82385 ,  H01L22/12 ,  H01L22/30

Abstract: A technique relates to fabricating a macro for measurements utilized in dual spacer, dual epitaxial transistor devices. The macro is fabricated according to a fabrication process. The macro is a test layout of a semiconductor structure having n-p bumps at junctions between NFET areas and PFET areas. Optical critical dimension (OCD) spectroscopy is performed to obtain the measurements of the n-p bumps on the macro. An amount of chemical mechanical polishing is determined to remove the n-p bumps on the macro based on the measurements of the n-p bumps on the macro. Chemical mechanical polishing is performed to remove the n-p bumps on the macro. The amount previously determined for the macro is utilized to perform chemical mechanical polishing for each of the dual spacer, dual epitaxial layer transistor devices having been fabricated under the fabrication process of the macro in which the fabrication process produced the n-p bumps.

Abstract translation: 技术涉及制造用于双间隔物，双外延晶体管器件中的测量的宏。 宏是根据制造工艺制造的。 该宏是在NFET区域和PFET区域之间的结处具有n-p个凸起的半导体结构的测试布局。 执行光临界尺度（OCD）光谱以获得宏观上的n-p凸块的测量。 基于宏观上的n-p凸块的测量，确定了一定量的化学机械抛光以去除宏观上的n-p凸块。 进行化学机械抛光以除去宏观上的n-p凸块。 先前为宏确定的量用于对在制造工艺产生n-p个凸块的宏的制造过程中制造的每个双间隔物，双外延层晶体管器件进行化学机械抛光。

公开(公告)号：US09431540B2

公开(公告)日：2016-08-30

申请号：US14288766

申请日：2014-05-28

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Chun-chen Yeh

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers.

Abstract translation: 制造半导体器件的方法包括在衬底上形成横向间隔开的半导体鳍片。 在半导体鳍片的端部附近和相邻的半导体鳍片之间的空间内形成至少一个电介质层。 在半导体翅片的端部处邻近最外半导体翅片形成一对侧壁间隔物。 去除该对侧壁间隔物之间​​的至少一个电介质层和半导体翅片的端部。 源极/漏极区域形成在该对侧壁间隔物之间​​。

公开(公告)号：US09406751B2

公开(公告)日：2016-08-02

申请号：US14296818

申请日：2014-06-05

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L29/08 ,  H01L27/12 ,  H01L29/786 ,  H01L21/84 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/786 ,  H01L29/78684

Abstract: A method for making a semiconductor device is provided. Raised source and drain regions are formed with a tensile strain-inducing material, after thermal treatment to form source drain extension regions, to thereby preserve the strain-inducing material in desired substitutional states.

Abstract translation: 提供一种制造半导体器件的方法。 在热处理之后，用拉伸应变诱导材料形成凸起的源极和漏极区域以形成源极漏极延伸区域，从而将应变诱导材料保持在期望的替代状态。

公开(公告)号：US20160181381A1

公开(公告)日：2016-06-23

申请号：US14577431

申请日：2014-12-19

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GlobalFoundries Inc

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/41783 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A FinFET device includes a semiconductor fin, a gate electrode extending over a channel of the fin and sidewall spacers on each side of the gate electrode. A dielectric material is positioned on each side of a bottom portion of said fin, with an oxide material on each side of the fin overlying the dielectric material. A recessed region, formed in the fin on each side of the channel region, is delimited by the oxide material. A raised source region fills the recessed region and extends from the fin on a first side of the gate electrode to cover the oxide material to a height which is in contact with the sidewall spacer. A raised drain region fills the recessed region and extends from the fin on a second side of the gate electrode to cover the oxide material to a height which is in contact with the sidewall spacer.

Abstract translation: FinFET器件包括半导体鳍片，在鳍片的沟道上延伸的栅极电极和在栅电极的每一侧上的侧壁间隔物。 电介质材料位于所述散热片的底部的每一侧上，其中在散热片的每侧的氧化物材料覆盖在电介质材料上。 在通道区域的每一侧的翅片上形成的凹陷区域由氧化物材料界定。 凸起的源极区域填充凹陷区域并且在栅电极的第一侧上从翅片延伸以将氧化物材料覆盖到与侧壁间隔物接触的高度。 凸起的漏极区域填充凹陷区域并且在栅电极的第二侧上从翅片延伸以将氧化物材料覆盖到与侧壁间隔物接触的高度。

公开(公告)号：US20160163850A1

公开(公告)日：2016-06-09

申请号：US14560255

申请日：2014-12-04

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GlobalFoundries Inc

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh ,  Xiuyu Cai

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L27/092 ,  H01L29/08

CPC classification number: H01L29/785 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/41758 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7848

Abstract: A FinFET transistor includes a fin of semiconductor material with a transistor gate electrode extending over a channel region. Raised source and drain regions of first epitaxial growth material extending from the fin on either side of the transistor gate electrode. Source and drain contact openings extend through a pre-metallization dielectric material to reach the raised source and drain regions. Source and drain contact regions of second epitaxial growth material extend from the first epitaxial growth material at the bottom of the source and drain contact openings. A metal material fills the source and drain contact openings to form source and drain contacts, respectively, with the source and drain contact regions. The drain contact region may be offset from the transistor gate electrode by an offset distance sufficient to provide a laterally diffused metal oxide semiconductor (LDMOS) configuration within the raised source region of first epitaxial growth material.

Abstract translation: FinFET晶体管包括具有在沟道区域上延伸的晶体管栅电极的半导体材料的鳍。 从晶体管栅电极的两侧的鳍延伸的第一外延生长材料的引出源区和漏区。 源极和漏极接触开口延伸穿过预金属化电介质材料以到达升高的源极和漏极区域。 第二外延生长材料的源极和漏极接触区域在源极和漏极接触开口的底部处从第一外延生长材料延伸。 金属材料填充源极和漏极接触开口，以分别与源极和漏极接触区域形成源极和漏极接触。 漏极接触区域可以从晶体管栅电极偏移足以在第一外延生长材料的升高的源极区域内提供横向扩散的金属氧化物半导体（LDMOS）配置的偏移距离。

公开(公告)号：US20150380258A1

公开(公告)日：2015-12-31

申请号：US14314384

申请日：2014-06-25

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Chun-chen Yeh ,  Kejia Wang

IPC: H01L21/308 ,  H01L29/205 ,  H01L29/78

CPC classification number: H01L29/205 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods and structures for forming fin structures whilst controlling the height of the fin structures with high uniformity across large areas are described. According to some aspects, a multi-layer structure comprising a first etch-stop layer and a second etch-stop layer separated from a substrate and from each other by spacer layers is formed on a substrate. Trenches may be formed through the first and second etch-stop layers. A buffer layer may be formed in the trenches, filling the trenches to a level approximately at a position of the first etch-stop layer. A semiconductor layer may be formed above the buffer layer and etched back to the second etch-stop layer to form semiconductor fins of highly uniform heights.

Abstract translation: 描述了形成翅片结构的方法和结构，同时在大面积上以高均匀性控制翅片结构的高度。 根据一些方面，在衬底上形成包括由衬底分离并通过间隔层彼此分离的第一蚀刻停止层和第二蚀刻停止层的多层结构。 沟槽可以通过第一和第二蚀刻停止层形成。 可以在沟槽中形成缓冲层，将沟槽填充到大致在第一蚀刻停止层的位置处的水平。 半导体层可以形成在缓冲层的上方并被回蚀刻到第二蚀刻停止层以形成高均匀高度的半导体鳍片。

公开(公告)号：US09219078B2

公开(公告)日：2015-12-22

申请号：US13865795

申请日：2013-04-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc. ,  GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Qing Liu ,  Nicolas Loubet ,  Scott Luning

IPC: H01L27/12 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L21/84 ,  H01L29/10

CPC classification number: H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/4966

Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.

Abstract translation: 一种用于半导体制造的方法包括在包括至少一个硅锗（SiGe）沟道区的衬底上提供沟道区，所述衬底包括包括第一区和第二区的多个区域。 对于第一区域中的第一n型场效应晶体管（NFET）和第一p型场效应晶体管（PFET）以及第二区域中的第二NFET和第二PFET形成栅极结构， 第一PFET形成在SiGe沟道区上。 用于第一NFET的栅极结构包括具有第一功函数的栅极材料，并且用于第一PFET，第二NFET和第二PFET的栅极结构包括具有第二功函数的栅极材料，使得提供多阈值电压器件。

公开(公告)号：US09202920B1

公开(公告)日：2015-12-01

申请号：US14447727

申请日：2014-07-31

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Chun-chen Yeh ,  Ruilong Xie ,  Xiuyu Cai

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848

Abstract: Methods and structures for forming short-channel finFETs with vertical and abrupt source and drain junctions are described. During fabrication, source and drain regions of the finFET may be recessed vertically and laterally under gate spacers. A buffer having a high dopant density may be formed on vertical sidewalls of the channel region after recessing the fin. Raised source and drain structures may be formed at the recessed source and drain regions. The raised source and drain structures may impart strain to the channel region.

Abstract translation: 描述了用于形成具有垂直和突然的源极和漏极结的短沟道finFET的方法和结构。 在制造期间，finFET的源极和漏极区域可以在栅极间隔物下方垂直和横向地凹陷。 具有高掺杂浓度的缓冲器可以在凹陷鳍片之后形成在沟道区域的垂直侧壁上。 可以在凹陷的源极和漏极区域形成升高的源极和漏极结构。 升高的源极和漏极结构可能对沟道区域施加应变。