Abstract:
Photoluminescence from a sample detector is detected using an array of photo-sensitive detectors. At least one first photo-sensitive detector of the array is provided with a first type of linear polarization filter and at least one second photo-sensitive detector is provided with a second type of linear polarization filter. The first type of linear polarization filter has a plane of polarization which is at angled with respect to a plane of polarization of said second type of polarization filter.
Abstract:
An electronic device disclosed herein includes a single photon avalanche diode (SPAD) configured to detect an incoming photon and to generate a first pulse signal in response thereto. Pulse shaping circuitry is configured to generate a second pulse signal from the first pulse signal by high pass filtering the first pulse signal. The pulse shaping circuitry includes a transistor drain-source coupled between a first node and a reference node, and a capacitor coupling the first node to an anode of the SPAD.
Abstract:
An apparatus includes an illumination source configured to emit light when driven with a current greater than a threshold current and driver circuitry configured to drive the illumination source with a controllable current. The driver circuit controlled by at least a first input value. At least one illumination detector is configured to detect light emitted by the illumination source and monitor circuitry is configured to receive an output from the illumination detector and provide the first input value.
Abstract:
A single photon avalanche diode based range detecting apparatus includes a reference array of single photon avalanche diodes configured to receive light from an illumination source via an internally coupled path. A return array of single photon avalanche diodes is configured to receive light from the illumination source via an external free space path. A calibration pulse generator is configured to generate a calibration signal pulse. Readout circuitry is configured to receive an output of the reference array via a reference signal path, an output of the return array via a return signal path, and an output of the calibration pulse generator via a calibration signal path. The readout circuitry is configured to determine a delay difference value between the reference signal path and the return signal path based on the output of the calibration pulse generator via the calibration signal path.
Abstract:
An image sensor includes an analog-to-digital converter receiving a pixel signal output. The converter includes a first inverting amplifier circuit having an input and an output, the first inverting amplifier circuit including a first bias circuit having a control node and configured to source current for first inverting amplifier circuit operation. The converter further includes a second inverting amplifier circuit having an input and an output, the second inverting amplifier circuit including a second bias circuit having a control node and configured to source current for second inverting amplifier circuit operation. The output of the first inverting amplifier circuit is coupled to the input of the second inverting amplifier circuit. A positive feedback circuit couples the output of the second inverting amplifier circuit to the control node of the first bias circuit.
Abstract:
An array of photon sensitive devices is configured to provide outputs. Pulse shaping circuits operate to shape a respective output of the array in a normal mode of operation and shape a calibration signal in a calibration mode of operation.
Abstract:
An image sensor includes an analog-to-digital converter receiving a pixel signal output. The converter includes a first inverting amplifier circuit having an input and an output, the first inverting amplifier circuit including a first bias circuit having a control node and configured to source current for first inverting amplifier circuit operation. The converter further includes a second inverting amplifier circuit having an input and an output, the second inverting amplifier circuit including a second bias circuit having a control node and configured to source current for second inverting amplifier circuit operation. The output of the first inverting amplifier circuit is coupled to the input of the second inverting amplifier circuit. A positive feedback circuit couples the output of the second inverting amplifier circuit to the control node of the first bias circuit.