公开(公告)号：US11282792B2

公开(公告)日：2022-03-22

申请号：US16805890

申请日：2020-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Kun Jee ,  Hae-Jung Yu ,  Sangwon Kim ,  Un-Byoung Kang ,  Jongho Lee ,  Dae-Woo Kim ,  Wonjae Lee

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/498

Abstract: A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the second semiconductor chip, and a plurality of dummy pads disposed outside of an area occupied by the first semiconductor chip or the second semiconductor chip from a top-down view and disposed on the top surface of the interposer substrate. Each pad of the first plurality of signal pads and the second plurality of signal pads is configured to transfer signals between the interposer substrate and a respective semiconductor chip, and each pad of the dummy pads is not configured to transfer signals between the interposer substrate and any semiconductor chip disposed thereon.

公开(公告)号：US20210358875A1

公开(公告)日：2021-11-18

申请号：US17155657

申请日：2021-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuekjae Lee ,  Jongho Lee ,  Jihoon Kim ,  Taehun Kim ,  Sangcheon Park ,  Jinkyeong Seol ,  Sanghoon Lee

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.

公开(公告)号：US11157264B2

公开(公告)日：2021-10-26

申请号：US16981489

申请日：2019-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongho Lee ,  Heechae Yoon ,  Byungchul Kim ,  Jiseong Lee ,  Junghoon Cho

IPC: G06F8/65 ,  G06F8/71 ,  G06F9/4401 ,  G06F12/06

Abstract: An electronic device is provided. The electronic device includes a first memory including a boot area, a kernel area, and a recovery area, a second memory configured to load data corresponding to at least one from among the boot area, the kernel area, and the recovery area included in the first memory, a communication module, and a processor electrically connected to the communication module, the first memory, and the second memory. The first memory includes instructions that cause, when executed, the processor to download data in the first memory through the communication module, when there is a request for updating the downloaded data, perform rebooting, when performing the rebooting, confirm whether a new version of recovery data is included in the downloaded data, and when the new version of recovery data is included in the data, update the downloaded data on the basis of the new version of recovery data.

公开(公告)号：US10978374B2

公开(公告)日：2021-04-13

申请号：US16285480

申请日：2019-02-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunki Kim ,  Sangsoo Kim ,  Seung Hwan Kim ,  Kyung Suk Oh ,  Yongkwan Lee ,  Jongho Lee

IPC: H01L23/433 ,  H01L25/065 ,  H01L23/367 ,  H01L25/07 ,  H01L23/00

Abstract: Disclosed is a semiconductor package comprising a package substrate, a first semiconductor chip on the package substrate and including a first region and a second region, a second semiconductor chip on the first region, a heat radiation spacer on the second region, a third semiconductor chip supported by the second semiconductor chip and the heat radiation spacer, and a molding layer covering the first to third semiconductor chips and the heat radiation spacer.

公开(公告)号：US20200345311A1

公开(公告)日：2020-11-05

申请号：US16426225

申请日：2019-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Youngbeom KIM ,  Doohee Lee ,  Jongho Lee ,  Junki Lee ,  Sangyoung Zho

IPC: A61B5/00 ,  A61B5/055 ,  G01R33/50 ,  G01R33/56 ,  G06F17/50

Abstract: Provided are a magnetic resonance imaging (MRI) apparatus and method of operating the same, whereby a characteristic parameter value may be acquired from MR signal data via training using an artificial neural network (ANN) and a parametric map may be generated based on the acquired characteristic parameter value.

公开(公告)号：US20190027475A1

公开(公告)日：2019-01-24

申请号：US16137625

申请日：2018-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Dae Suk ,  Jongho Lee ,  Geumjong Bae

IPC: H01L27/092 ,  H01L29/786 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/417 ,  H01L23/535 ,  H01L29/423

Abstract: A semiconductor device includes an insulating layer on a substrate, a channel region on the insulating layer, a gate structure on the insulating layer, the gate structure crossing the channel region, source/drain regions on the insulating layer, the source/drain regions being spaced apart from each other with the gate structure interposed therebetween, the channel region connecting the source/drain regions to each other, and contact plugs connected to the source/drain regions, respectively. The channel region includes a plurality of semiconductor patterns that are vertically spaced apart from each other on the insulating layer, the insulating layer includes first recess regions that are adjacent to the source/drain regions, respectively, and the contact plugs include lower portions provided into the first recess regions, respectively.

公开(公告)号：US09640513B2

公开(公告)日：2017-05-02

申请号：US14682113

申请日：2015-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee ,  Chul-Yong Jang ,  Jongho Lee

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/367 ,  H01L25/10 ,  H01L23/13 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/29036 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014

Abstract: Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a first package having a first package substrate mounted with a lower semiconductor chip, and a second package having a second package substrate mounted with upper semiconductor chips. The second package substrate includes a chip region on which the upper semiconductor chips are mounted, and a connection region provided therearound. The chip region includes a first surface defining a first recess region and a second surface defining a first protruding portion. The upper semiconductor chips are mounted on opposite edges of the second surface and spaced apart from each other to have portions protruding toward the connection region beyond the chip region.