公开(公告)号：US20210143203A1

公开(公告)日：2021-05-13

申请号：US17157152

申请日：2021-01-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takayuki IKEDA ,  Naoto KUSUMOTO

IPC: H01L27/146 ,  H01L27/12

Abstract: An imaging device having a three-dimensional integration structure is provided. A first structure including a transistor including silicon in an active layer or an active region and a second structure including an oxide semiconductor in an active layer are fabricated. After that, the first and second structures are bonded to each other so that metal layers included in the first and second structures are bonded to each other; thus, an imaging device having a three-dimensional integration structure is formed.

公开(公告)号：US20200287050A1

公开(公告)日：2020-09-10

申请号：US16881187

申请日：2020-05-22

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takayuki IKEDA

IPC: H01L29/786 ,  H01L27/148 ,  H01L27/146 ,  H01L27/12

Abstract: An imaging element which is capable of obtaining a piece of image data by performing light exposure plural times is provided. In addition, an imaging element which is capable of obtaining image data with little noise is provided. Furthermore, an imaging device with reduced power consumption is provided. In an imaging element including a pixel, the pixel includes a photodiode, a transistor including an oxide semiconductor layer, a diode, and a charge retention portion. The polarity of an electrode of the photodiode which is connected to the transistor is the same as that of an electrode of the diode which is connected to the transistor.

公开(公告)号：US20190265770A1

公开(公告)日：2019-08-29

申请号：US16288934

申请日：2019-02-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA ,  Takayuki IKEDA ,  Shunpei YAMAZAKI

IPC: G06F1/32 ,  G06G7/00 ,  G06F1/3287

Abstract: The power consumption of an analog arithmetic circuit is reduced. The analog arithmetic circuit includes a plurality of first circuits. An output terminal of the k-th (k is a natural number) first circuit is connected to an input terminal of the k+1-th first circuit. Each of the first circuits includes a memory circuit which holds an analog signal, a second circuit which performs arithmetic processing using the analog signal, a switch which controls power supply to the second circuit, and a controller. The conduction state of the switch included in the k-th first circuit is controlled by the controller included in the k+1-th first circuit. The arithmetic processing performed by the second circuit included in the k+1-th first circuit is started by the controller included in the k+1-th first circuit.

公开(公告)号：US20180009403A1

公开(公告)日：2018-01-11

申请号：US15544087

申请日：2016-01-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Takayuki IKEDA ,  Yoshiyuki KUROKAWA

IPC: B60R21/0134 ,  G06K9/00 ,  B60R21/01

CPC classification number: B60R21/0134 ,  B60R21/00 ,  B60R21/013 ,  B60R2021/01013 ,  B60R2021/01211 ,  G06K9/00791 ,  G06T2207/30252

Abstract: An occupant protection device which can protect an occupant without delay is provided. An image taken by an imaging device is analyzed to judge whether there is an object approaching the subject car. In the case where a collision between the object and the subject car is judged to be inevitable, an airbag device is activated before the collision, whereby the occupant can be protected without delay. By using selenium for a light-receiving element of the imaging device, an accurate image can be obtained even under low illuminance. Imaging in a global shutter system leads to an accurate image with little distortion. This enables more accurate image analysis.

公开(公告)号：US20170337867A1

公开(公告)日：2017-11-23

申请号：US15596138

申请日：2017-05-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Takayuki IKEDA

IPC: G09G3/20 ,  G09G5/14 ,  B60K35/00 ,  B60K37/02

Abstract: An object is to provide a display system with a novel structure and a vehicle. The display system includes a display and a control IC. The control IC includes a frame memory, an arithmetic circuit, and a memory circuit. The display has a curved display surface. The frame memory has a function of holding first image data dedicated to displaying an image on a flat surface. The memory circuit has a function of storing shape data on the display. The arithmetic circuit has a function of converting first coordinates of the curved display surface into second coordinates of the flat surface included in the first image data, by performing arithmetic operation in accordance with the shape data. The arithmetic circuit has a function of outputting the first image data stored in the frame memory to the display as second image data on the basis of the second coordinates.

公开(公告)号：US20170309856A1

公开(公告)日：2017-10-26

申请号：US15520647

申请日：2015-10-20

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Takayuki IKEDA ,  Yoshiyuki KUROKAWA

IPC: H01L51/50 ,  H01L51/00 ,  C09K11/59 ,  H01L51/42 ,  C09K11/06 ,  H01L51/05

CPC classification number: H01L51/5012 ,  B81B7/008 ,  B81B2201/042 ,  B81C1/00246 ,  B81C2203/0735 ,  C09K11/06 ,  C09K11/59 ,  G02B26/02 ,  G02B26/085 ,  H01L29/786 ,  H01L51/0051 ,  H01L51/0508 ,  H01L51/4226

Abstract: A highly reliable micromachine, display element, or the like is provided. As a micromachine or a transistor including the micromachine, a transistor including an oxide semiconductor in a semiconductor layer where a channel is formed is used. For example, a transistor including an oxide semiconductor is used as at least one transistor in one or a plurality of transistors driving a micromachine.

公开(公告)号：US20170069673A1

公开(公告)日：2017-03-09

申请号：US15254255

申请日：2016-09-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takayuki IKEDA

IPC: H01L27/146 ,  H04N5/3745 ,  H04N5/353

CPC classification number: H01L27/14616 ,  H01L27/14607 ,  H01L27/14609 ,  H01L27/1462 ,  H01L27/14627 ,  H01L27/14641 ,  H01L27/14696 ,  H04N5/37457

Abstract: An imaging device which can perform imaging with a global shutter system and in which transistors are shared by pixels is provided. The imaging device includes first and second photoelectric conversion elements and first to sixth transistors. Active layers of the first to fourth transistors each include an oxide semiconductor. The imaging device has a configuration in which a reset transistor and an amplifier transistor are shared by a plurality of pixels and can perform imaging with a global shutter system. In addition, the imaging device can be used as a high-speed camera.

Abstract translation: 提供了能够利用全局快门系统执行成像并且由像素共享晶体管的成像装置。 成像装置包括第一和第二光电转换元件和第一至第六晶体管。 第一至第四晶体管的有源层各自包括氧化物半导体。 成像装置具有其中复位晶体管和放大器晶体管被多个像素共享并且可以使用全局快门系统执行成像的配置。 此外，成像装置可以用作高速摄像机。

公开(公告)号：US20160380630A1

公开(公告)日：2016-12-29

申请号：US15191763

申请日：2016-06-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro KOZUMA ,  Yoshiyuki KUROKAWA ,  Takayuki IKEDA ,  Takeshi AOKI

IPC: H03K19/00 ,  H03K19/173 ,  H03K19/177 ,  H01L27/12 ,  H01L29/786

CPC classification number: H03K19/0013 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/7869 ,  H03K19/09441 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17748 ,  H03K19/1776

Abstract: A programmable logic device includes a plurality of programmable logic elements (PLE) whose electrical connection is controlled by first configuration data. Each of The PLEs includes an LUT in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data, an FF to which the output signal of the LUT is input, and an MUX. The MUX includes at least two switches each including first and second transistor. A signal including third configuration data is input to a gate of the second transistor through the first transistor. The output signal of the LUT or an output signal of the FF is input to one of a source and a drain of the second transistor.

公开(公告)号：US20160322975A1

公开(公告)日：2016-11-03

申请号：US15146981

申请日：2016-05-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takayuki IKEDA ,  Yoshiyuki KUROKAWA

IPC: H03K19/177 ,  H01L27/12 ,  H01L29/24 ,  H03K19/173 ,  H01L29/786

CPC classification number: H03K19/1776 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/78648 ,  H01L29/7869 ,  H03K19/1735 ,  H03K19/177 ,  H03K19/17728 ,  H03K19/17764 ,  H03K19/17792

Abstract: Provided is a programmable logic device that includes logic elements arranged in a plurality of columns. Wirings connecting logic elements are arranged between the plurality of columns. Switch circuits that control electrical connections between the wirings and the logic elements are also arranged between the plurality of columns. Each of the switch circuit selects an electrical connection between one of the wirings and an input terminal of one of the logic elements in accordance with configuration data.

公开(公告)号：US20160269032A1

公开(公告)日：2016-09-15

申请号：US15163817

申请日：2016-05-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA ,  Takayuki IKEDA

IPC: H03K19/177 ,  H03K19/0944 ,  H03K19/173

CPC classification number: H03K19/1776 ,  H03K19/0944 ,  H03K19/1737 ,  H03K19/177 ,  H03K19/17772 ,  H03K19/17776

Abstract: A PLD in which a configuration memory is formed using a nonvolatile memory with a small number of transistors and in which the area of a region where the configuration memory is disposed is reduced is provided. Further, a PLD that is easily capable of dynamic reconfiguration and has a short startup time is provided. A programmable logic device including a memory element, a selector, and an output portion is provided. The memory element includes a transistor in which a channel is formed in an oxide semiconductor film, and a storage capacitor and an inverter which are connected to one of a source and a drain of the transistor. The inverter is connected to the selector. The selector is connected to the output portion.