中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

142 records (took 0.021 seconds)

    RUGGED LDMOS WITH DRAIN-TIED FIELD PLATE
    64.
    发明申请
    RUGGED LDMOS WITH DRAIN-TIED FIELD PLATE 有权

    公开(公告)号：US20220149186A1

    公开(公告)日：2022-05-12

    申请号：US17092485

    申请日：2020-11-09

    Applicant: Texas Instruments Incorporated

    Inventor： Henry Litzmann Edwards ,  Gang Xue

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/08 ,  H01L21/762

    Abstract: A semiconductor device including a substrate having a semiconductor layer containing a laterally diffused metal oxide semiconductor (LDMOS) transistor, including a body region of a first conductivity type and a drift region of an opposite conductivity type. A gate dielectric layer over a channel region of the body, the gate dielectric extending over a junction between a body region and the drift region with a gate electrode on the gate dielectric and a drain contact in the drain drift region, having the second conductivity type. A field relief dielectric layer on the drain drift region extending from the drain region to the gate dielectric, having a thickness greater than the gate dielectric layer. A drain-tied field plate on the field relief dielectric, the drain-tied field plate extending from the drain region toward the gate with an electrical connection between the drain-tied field plate and the drain region.

    BCD IC WITH GATE ETCH AND SELF-ALIGNED IMPLANT INTEGRATION
    65.
    发明申请
    BCD IC WITH GATE ETCH AND SELF-ALIGNED IMPLANT INTEGRATION 有权

    公开(公告)号：US20220068649A1

    公开(公告)日：2022-03-03

    申请号：US17411431

    申请日：2021-08-25

    Applicant: Texas Instruments Incorporated

    Inventor： Mona M. Eissa ,  Jason R. Heine ,  Pushpa Mahalingam ,  Henry Litzmann Edwards ,  James Robert Todd ,  Alexei Sadovnikov

    IPC: H01L21/266 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423

    Abstract: A method of fabricating an IC includes providing a substrate including a semiconductor surface having well diffusions for a plurality of devices including bipolar, complementary metal oxide semiconductor (CMOS), and double-diffused MOS (DMOS) devices. A polysilicon layer is deposited on a dielectric layer over the semiconductor surface, an anti-reflective coating (ARC) layer is formed on the polysilicon layer, and a photoresist pattern is formed on the ARC layer. The ARC layer is etched in areas exposed by the photoresist pattern to define areas including gate areas having the ARC layer on the polysilicon layer. The photoresist pattern is removed. Polysilicon etching is performed in areas lacking the ARC layer to form polysilicon gates having a remaining ARC portion of the ARC layer thereon. A self-aligned ion implant uses the remaining ARC portion as an additional implant blocking layer for the polysilicon gates, and the remaining ARC portion is stripped.

    LDMOS device with body diffusion self-aligned to gate
    68.
    发明授权
    LDMOS device with body diffusion self-aligned to gate 有权

    公开(公告)号：US10903356B2

    公开(公告)日：2021-01-26

    申请号：US15865028

    申请日：2018-01-08

    Applicant: Texas Instruments Incorporated

    Inventor： Henry Litzmann Edwards ,  Binghua Hu ,  James Robert Todd

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/167 ,  H01L21/265 ,  H01L21/324 ,  H01L29/423

    Abstract: A laterally diffused metal oxide semiconductor (LDMOS) device includes a substrate having a p-epi layer thereon, a p-body region in the p-epi layer and an ndrift (NDRIFT) region within the p-body to provide a drain extension region. A gate stack includes a gate dielectric layer over a channel region in the p-body region adjacent to and on respective sides of a junction with the NDRIFT region. A patterned gate electrode is on the gate dielectric. A DWELL region is within the p-body region. A source region is within the DWELL region, and a drain region is within the NDRIFT region. An effective channel length (Leff) for the LDMOS device is 75 nm to 150 nm which evidences a DWELL implant that utilized an edge of the gate electrode to delineate an edge of a DWELL ion implant so that the DWELL region is self-aligned to the gate electrode.

    DRAIN EXTENDED NMOS TRANSISTOR
    70.
    发明申请
    DRAIN EXTENDED NMOS TRANSISTOR 审中-公开

    公开(公告)号：US20190172946A1

    公开(公告)日：2019-06-06

    申请号：US15830856

    申请日：2017-12-04

    Applicant: Texas Instruments Incorporated

    Inventor： Xiaoju Wu ,  Robert James Todd ,  Henry Litzmann Edwards

    IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L21/762 ,  H01L21/265 ,  H01L21/324 ,  H01L21/225 ,  H01L21/285 ,  H01L21/74

    Abstract: A semiconductor device includes a NMOS transistor with a back gate connection and a source region disposed on opposite sides of the back gate connection. The source region and back gate connection are laterally isolated by an STI oxide layer which surrounds the back gate connection. The NMOS transistor has a gate having a closed loop configuration, extending partway over a LOCOS oxide layer which surrounds, and is laterally separated from, the STI oxide layer. A lightly-doped drain layer is disposed on opposite sides of the NMOS transistor, extending under the LOCOS oxide layer to a body region of the NMOS transistor. The LOCOS oxide layer is thinner than the STI oxide layer, so that the portion of the gate over the LOCOS oxide layer provides a field plate functionality. The NMOS transistor may optionally be surrounded by an isolation structure which extends under the NMOS transistor.

Patent Agency Ranking