Abstract:
The present disclosure provides methods for etching through-silicon vias (TSVs) in a substrate. The method employs a cyclic polymer passivation layer deposition, depassivation process and plasma etching process. By alternating the duration performed in the plasma etching process and the polymer passivation deposition process during the TSVs formation process, a good sidewall profile and via depth control may be obtained.
Abstract:
A system and method for micro computed tomography (CT) reconstruction of position scan data of planar objects, such as stacked integrated circuit chips and/or PCB, that automatically determines object orientation is disclosed for a preferred orientation of the reconstructed images. The object orientation of the sinogram of the scanning data is determined such that the reconstruction may be performed with any starting position. Additionally, planar object scan reconstructions with either a higher resolution in the thickness dimension without increasing the total computation resource or a faster processing speed under a given resolution in the thickness dimension may be achieved. The tilting angle with respect to the rotation axis may also be determined to perform a image rotation after a multi-slice reconstruction or cone-beam reconstruction.
Abstract:
In one example, a Cable Modem Termination System (CMTS) sends first bandwidth allocation messages to a first upstream transmit interface on a cable modem and send second bandwidth allocation messages to a second upstream transmit interface on the cable modem. The bandwidth allocation messages indicate transmit windows for the cable modem to range over the interfaces. The transmit windows included in the first bandwidth allocation messages are spaced based on receipt of ranging requests from the second upstream transmit interface, and the transmit windows included in the second bandwidth allocation messages are spaced based on receipt of ranging requests from the first upstream transmit interface.
Abstract:
A computer-implemented process is provided for reorienting a three-dimensional (3D) scan image of an object. The object has a generally flat surface. The image is constructed from image data obtained during rotation of the object about a rotation axis, which intersects the plane of the flat surface at an angle. Axial slices of the scan image are obtained, each of which represents a slice of the object that is perpendicular to the rotation axis and comprises a line representing the flat surface of the object. The axial slices are shifted to align lines representing the flat surface in different axial slices, thus forming a reoriented 3D image. Alternatively, an axial tilt angle is determined from the positions of these lines and the image is rotated by the determined angle to form a reoriented 3D image.
Abstract:
Inclusions in a transparent panel (5) are detected by placing a light transmissive interface (3) in contact with the panel (5), and transmitting a beam of light (1) through interface (3) into panel (5). Within the panel (5), the light beam (7) propagates along a path including total internal reflections at surfaces of panel (5). When the light beam (1) intercepts inclusions (10) or other defects at least some of it is scattered, and leaves the panel (5). This scattered light is then observed. Thus, a large zone of the panel (5) can be inspected, with light only being detected in the case that it arises from scattering by inclusions or other defects.
Abstract:
Techniques for scrolling through displayed information are disclosed. For instance, an apparatus includes a scrolling management module to set one or more automatic scrolling preferences, and an application to output a content item in accordance with the one or more automatic scrolling preferences. Examples of such scrolling preferences include scrolling speeds, designated input mechanism(s) to adjust scrolling, and the activation/deactivation of orientation-based scrolling.
Abstract:
A keyboard, video monitor and mouse (KVM) Universal Serial Bus (USB) Internet protocol (IP) server interface pod (SIP) allows access to selected ones of a plurality of servers by a remotely located keyboard, video monitor and mouse. In addition, remote mounting of a USB device to the selected server is also possible. A digital KVM USB switch may be used for routing the remotely located keyboard, video monitor, mouse and USB device to the KVM USB IP SIP. The digital KVM USB switch also is coupled to a KVM USB IP interface. The KVM USB IP interface is located with and connected to the remotely located keyboard, video monitor, mouse and USB device. The KVM USB IP interface may be coupled to the digital KVM USB switch over a local area network (LAN), wide area network (WAN), or Internet.
Abstract translation:键盘,视频监视器和鼠标(KVM)通用串行总线(USB)互联网协议(IP)服务器接口盒(SIP)允许通过位于远程的键盘,视频监视器和鼠标来访问多个服务器中的选定的服务器。 此外,还可以将USB设备远程安装到所选择的服务器。 数字KVM USB开关可用于将远程位置的键盘,视频监视器,鼠标和USB设备路由到KVM USB IP SIP。 数字KVM USB开关也耦合到KVM USB IP接口。 KVM USB IP接口位于远程位置的键盘,视频监视器,鼠标和USB设备上。 KVM USB IP接口可以通过局域网(LAN),广域网(WAN)或互联网耦合到数字KVM USB交换机。
Abstract:
Inclusions in a transparent panel (5) are detected by placing a light transmissive interface (3) in contact with the panel (5), and transmitting a beam of light (1) through interface (3) into panel (5). Within the panel (5), the light beam (7) propagates along a path including total internal reflections at surfaces of panel (5). When the light beam (1) intercepts inclusions (10) or other defects at least some of it is scattered, and leaves the panel (5). This scattered light is then observed. Thus, a large zone of the panel (5) can be inspected, with light only being detected in the case that it arises from scattering by inclusions or other defects.
Abstract:
The invention relates to an intra-tile buffering system for a field programmable gate array. The field programmable gate array comprises a field programmable gate array tile comprising a number of rows and a number of columns. Each row has a left end and a right end, and each column has a top end and a bottom end. Each row comprises a plurality of functional groups with an interface group located at said right end and said left end. Each column comprises a plurality of functional groups with an interface group located at said top end and said bottom end. A primary routing structure is coupled to said functional groups and interface groups and configured to receive primary output signals, route primary output signals within said at least one field programmable gate array tile, and provide primary input signals to said functional groups and interface groups. Each functional group is configured to receive a primary input signal, perform a logic operation, and generate a primary output signal. Each interface group is configured to transfer signals from said primary routing structure to outside of said at least one field programmable gate array tile, and includes a plurality of input multiplexers configured to select signals received from outside of said at least one field programmable gate array tile and provide signals to the primary routing structure inside said at least one field programmable gate array tile. Said primary routing structure comprises a horizontal bus coupled to each row of functional groups, a vertical bus coupled to each column of functional groups, a horizontal buffer coupled to each horizontal bus and spaced every Nth column of functional groups, where N is an integer, and a vertical buffer coupled to each horizontal bus and spaced every Mth row of functional groups, where M is an integer.
Abstract:
An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a third set of routing conductors, in addition to a first set of routing conductors and a second set of routing conductors and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive tertiary input signals as well as regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the first FPGA tile, and provide input signals to the third set of input ports of the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside of the first FPGA tile.