公开(公告)号：US20180247943A1

公开(公告)日：2018-08-30

申请号：US15889182

申请日：2018-02-05

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Shih-Fang Tzou ,  Chien-Ting Ho ,  Ying-Chiao Wang ,  Yu-Ching Chen ,  Hui-Ling Chuang ,  Kuei-Hsuan Yu

IPC: H01L27/108

CPC classification number: H01L27/10855 ,  H01L27/10814 ,  H01L27/10823

Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.

公开(公告)号：US20180226408A1

公开(公告)日：2018-08-09

申请号：US15452746

申请日：2017-03-08

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Ying-Chiao Wang ,  Tsung-Ying Tsai ,  Kai-Ping Chen ,  Chien-Ting Ho

IPC: H01L27/108 ,  H01L23/528

CPC classification number: H01L27/10885 ,  H01L23/5283 ,  H01L27/10897

Abstract: A semiconductor device includes a substrate, plural active areas, plural bit lines and plural dummy bit lines. The substrate includes a cell region and a periphery region, and the active areas are defined on the substrate. The bit lines are disposed on the substrate, within the cell region and across the active areas. The dummy bit lines are disposed at a side of the bit lines, wherein the dummy bit lines are in contact with each other and have different pitches therebetween.

公开(公告)号：US09773790B1

公开(公告)日：2017-09-26

申请号：US15456605

申请日：2017-03-13

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chien-Ting Ho ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Yu-Chieh Lin

IPC: H01L27/108 ,  H01L29/423 ,  H01L29/45

CPC classification number: H01L27/10823 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10897

Abstract: A semiconductor device includes a substrate including at least a memory region defined therein and a plurality of memory cells formed in the memory region, a plurality of first connecting structures, a plurality of second connecting structures, a plurality of dummy nodes respectively disposed on the first connecting structures, and a plurality of first storage nodes respectively disposed on the second connecting structures. The first connecting structures respectively include a conductive portion and a first metal portion, and the second connecting structures respectively include the conductive portion and a second metal portion. The first metal portion and the second metal portion include the same material. And the first metal portion and the second metal portion include different heights.