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61.发明申请公开(公告)号：US20140045105A1
公开(公告)日：2014-02-13
申请号：US14065443
申请日：2013-10-29
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chia-Wei Huang , Ming-Jui Chen , Chun-Hsien Huang
IPC: G03F1/76
CPC classification number: G03F1/76 , G03F1/70 , G06F17/5068 , G06F17/5081 , G06F19/00 , G06F2217/12 , G21K5/00 , H01L21/31144 , H01L21/76811 , H01L21/76816 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
Abstract: A method for fabricating a semiconductor layout includes providing a first layout having a plurality of line patterns and a second layout having a plurality of connection patterns, defining at least a first to-be-split pattern overlapping with the connection pattern among the line patterns, splitting the first to-be-split pattern at where the first to-be-split pattern overlapping with the connection pattern, decomposing the first layout to form a third layout and a fourth layout, and outputting the third layout and the further layout to a first mask and a second mask respectively.
Abstract translation: 一种用于制造半导体布局的方法包括提供具有多个线图案的第一布局和具有多个连接图案的第二布局，所述多个连接图案定义与线图案中的连接图案重叠的至少第一分割图案， 将第一待分割图案分割成与连接图案重叠的第一待分割图案，分解第一布局以形成第三布局和第四布局，并将第三布局和其他布局输出到 第一掩模和第二掩模。
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公开(公告)号：US20250095724A1
公开(公告)日：2025-03-20
申请号：US18966047
申请日：2024-12-02
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Hsien Huang , Yu-Tse Kuo , Shu-Ru Wang , Li-Ping Huang , Yu-Fang Chen , Chun-Yen Tseng , Tzu- Feng Chang , Chun-Chieh Chang
IPC: G11C11/412 , H01L29/66 , H01L29/78 , H10B10/00
Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.
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公开(公告)号：US12063791B2
公开(公告)日：2024-08-13
申请号：US17952327
申请日：2022-09-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Yen Tseng , Shu-Ru Wang , Yu-Tse Kuo , Chang-Hung Chen , Yi-Ting Wu , Shu-Wei Yeh , Ya-Lan Chiou , Chun-Hsien Huang
Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region and a second cell region and a diffusion region on the substrate extending through the first cell region and the second cell region. Preferably, the diffusion region includes a first H-shape and a second H-shape according to a top view.
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公开(公告)号：US20240161818A1
公开(公告)日：2024-05-16
申请号：US18071658
申请日：2022-11-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Hsien Huang , Yu-Tse Kuo , Shu-Ru Wang , Li-Ping Huang , Yu-Fang Chen , Chun-Yen Tseng , Tzu-Feng Chang , Chun-Chieh Chang
IPC: G11C11/412 , H01L29/66 , H01L29/78 , H10B10/00
CPC classification number: G11C11/412 , H01L27/1104 , H01L29/6681 , H01L29/7851
Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.
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公开(公告)号：US11943935B2
公开(公告)日：2024-03-26
申请号：US17952337
申请日：2022-09-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Yen Tseng , Shu-Ru Wang , Yu-Tse Kuo , Chang-Hung Chen , Yi-Ting Wu , Shu-Wei Yeh , Ya-Lan Chiou , Chun-Hsien Huang
Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.
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Patent Agency Ranking
公开(公告)号：US11475953B1
公开(公告)日：2022-10-18
申请号：US17377396
申请日：2021-07-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Yen Tseng , Yu-Tse Kuo , Shu-Ru Wang , Chun-Hsien Huang , Hsin-Chih Yu , Meng-Ping Chuang , Li-Ping Huang
Abstract: The invention provides a semiconductor layout pattern, the semiconductor layout pattern includes a substrate, a plurality of ternary content addressable memories (TCAM) are arranged on the substrate, the layout of at least two TCAM is mirror symmetric with each other along an axis of symmetry, and the two TCAM are connected to the same search line (SL) together.
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公开(公告)号：US11170854B2
公开(公告)日：2021-11-09
申请号：US17114373
申请日：2020-12-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Hsien Huang , Ching-Cheng Lung , Yu-Tse Kuo , Shu-Ru Wang , Chun-Yen Tseng
Abstract: A layout pattern of a two-port ternary content addressable memory (TCAM) includes a first storage unit, a second storage unit, a first comparison circuit and a second comparison circuit. The first comparison circuit and the second comparison circuit are positioned in a first side area of a side and a second side area of another side of the layout pattern, respectively. The first storage unit and the second storage unit are positioned in a first middle area and a second middle area between the first side area and the second side area, respectively. The first storage unit is connected to the first comparison circuit through a first gate structure and connected to the second comparison circuit through a second gate structure. The second storage unit is connected to the first comparison circuit through a third gate structure and connected to the second comparison circuit through a fourth gate structure.
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公开(公告)号：US10978122B1
公开(公告)日：2021-04-13
申请号：US16796953
申请日：2020-02-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Yen Tseng , Yu-Tse Kuo , Chang-Hung Chen , Shu-Ru Wang , Ya-Lan Chiou , Chun-Hsien Huang , Chih-Wei Tsai , Hsin-Chih Yu , Yi-Ting Wu , Cheng-Tung Huang , Jen-Yu Wang , Jhen-Siang Wu , Po-Chun Yang , Yung-Ching Hsieh , Jian-Jhong Chen , Bo-Chang Li
Abstract: A memory includes (n−1) non-volatile cells, (n−1) bit lines and a current driving circuit. Each of the (n−1) non-volatile cells includes a first terminal and a second terminal. An ith bit line of the (n−1) bit lines is coupled to a first terminal of an ith non-volatile cell of the (n−1) non-volatile cells. The current driving circuit includes n first transistors coupled to the (n−1) non-volatile cells.
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公开(公告)号：US10559573B2
公开(公告)日：2020-02-11
申请号：US16162340
申请日：2018-10-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Shu-Ru Wang , Ching-Cheng Lung , Yu-Tse Kuo , Chien-Hung Chen , Chun-Hsien Huang , Li-Ping Huang , Chun-Yen Tseng , Meng-Ping Chuang
IPC: H01L27/11 , G11C11/412 , G11C5/06 , G11C8/14 , G11C7/18 , H01L27/02 , H01L27/12 , H01L27/092
Abstract: A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise a first fin structure, the PG2A and the PG2B comprise a second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2, the first local interconnection layer and the second local interconnection layer are monolithically formed structures respectively.
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70.发明申请公开(公告)号：US20190221238A1
公开(公告)日：2019-07-18
申请号：US15900811
申请日：2018-02-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Yen Tseng , Ting-Hao Chang , Ching-Cheng Lung , Yu-Tse Kuo , Shih-Hao Liang , Chun-Hsien Huang , Shu-Ru Wang , Hsin-Chih Yu
IPC: G11C5/02 , H01L27/108 , H01L27/105 , H01L27/11 , G11C11/409 , G11C11/419
CPC classification number: G11C5/02 , G11C11/409 , G11C11/419 , H01L27/1052 , H01L27/10802 , H01L27/1108 , H01L29/7869
Abstract: The present invention provides a memory device, the memory device includes a first region having a plurality of oxide semiconductor static random access memories (OSSRAM) arranged in a first direction, and each of the OSSRAMs comprising a static random access memory (SRAM) and at least an oxide semiconductor dynamic random access memory (DOSRAM), wherein the DOSRAM is connected to the SRAM, wherein each of the DOSRAMs comprises an oxide semiconductor gate (OSG), and each of the OSGs extending in a second direction perpendicular to the first direction, and an oxide semiconductor channel extending in the first direction, an oxide semiconductor gate connection extending in the first direction to connect each of the OSGs, and a word line, a Vcc connection line and a Vss connection line extend in the first direction and are connected to the SRAMs in each OSSRAM.
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