公开(公告)号：US10170481B2

公开(公告)日：2019-01-01

申请号：US15915026

申请日：2018-03-07

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Li-Wei Feng ,  Chien-Ting Ho ,  Tsung-Ying Tsai

IPC: H01L27/108 ,  H01L21/762 ,  H01L29/06

Abstract: A semiconductor memory device and a method of forming the same, the semiconductor memory device includes a substrate, a plurality of bit lines, a gate, a spacer layer and a first spacer. The substrate has a memory cell region and a periphery region, the a plurality of bit lines are disposed on the substrate, within the memory cell region, and the gate is disposed on the substrate, within the periphery. The spacer layer covers the bit lines and a sidewall of the gate. The first spacer is disposed at two sides of the gate, covers on the spacer layer.

公开(公告)号：US10169521B2

公开(公告)日：2019-01-01

申请号：US15479271

申请日：2017-04-04

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Yu-Cheng Tung ,  Chien-Ting Ho ,  Li-Wei Feng ,  Emily SH Huang

IPC: G06F17/00 ,  G06F17/50 ,  H01L27/02 ,  H01L27/108

Abstract: A method for forming a contact plug layout include following steps. (a) Receiving a plurality of active region patterns and a plurality of buried gate patterns that are parallel with each other, and each active region pattern overlaps two buried gate patterns to form two overlapping regions and one contact plug region in between the two overlapping regions in each active region pattern; and (b) forming a contact plug pattern in each contact plug region, the contact plug pattern respectively includes a parallelogram, and an included angle of the parallelogram is not equal to 90°. The contact plug pattern in each active region pattern partially overlaps the two buried gate pattern, respectively. The step (a) to the step (b) are implemented using a computer.

公开(公告)号：US10157744B2

公开(公告)日：2018-12-18

申请号：US15885827

申请日：2018-02-01

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Kai-Ping Chen ,  Kuei-Hsuan Yu ,  Chiu-Hsien Yeh ,  Li-Wei Feng

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/02 ,  H01L21/027 ,  H01L27/108

Abstract: A method for forming patterns of semiconductor device is provided in the present invention, with steps of filling up first self-assembly material in first openings in a dielectric layer, phase-separating the first self-assembly material to form a first portion and a second portion surrounding the first portion, removing the first portion and performing a first etch process to form a first mask pattern in a mask layer, forming a second dielectric layer and repeating the above steps to form a second mask pattern in the mask layer, wherein the second mask pattern is aligned with the first mask pattern to form a common mask pattern.

公开(公告)号：US20180323190A1

公开(公告)日：2018-11-08

申请号：US15610642

申请日：2017-06-01

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Chien-Ting Ho ,  Shih-Fang Tzou

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L21/823456 ,  H01L21/823481 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/66666

Abstract: A method for fabricating semiconductor device includes the steps of first forming a first trench and a second trench in a substrate and then forming a shallow trench isolation (STI) in the first trench, in which the STI comprises a top portion and a bottom portion and a top surface of the top portion is even with or higher than a bottom surface of the second trench. Next, a conductive layer is formed in the first trench and the second trench to form a first gate structure and a second gate structure.

公开(公告)号：US10103150B1

公开(公告)日：2018-10-16

申请号：US15585180

申请日：2017-05-03

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Yu-Cheng Tung ,  Li-Wei Feng

IPC: H01L27/108 ,  H01L23/528

Abstract: The present invention provides a semiconductor structure including a substrate defining a memory cell region and a peripheral region, a periphery gate stacking structure located within the peripheral region, wherein the periphery gate stacking structure includes at least a first gate layer, and a second gate layer disposed on the first gate layer. The semiconductor structure further includes a cell stacking structure located within the memory cell region, the cell stacking structure having at least a first insulating layer partially disposed in the substrate, a top surface of the first insulating layer being higher than a top surface of the substrate, and the top surface of the first insulating layer and a top surface of the first gate layer being on a same level.

公开(公告)号：US20180294266A1

公开(公告)日：2018-10-11

申请号：US15585180

申请日：2017-05-03

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Yu-Cheng Tung ,  Li-Wei Feng

IPC: H01L27/108 ,  H01L23/528

Abstract: The present invention provides a semiconductor structure including a substrate defining a memory cell region and a peripheral region, a periphery gate stacking structure located within the peripheral region, wherein the periphery gate stacking structure includes at least a first gate layer, and a second gate layer disposed on the first gate layer. The semiconductor structure further includes a cell stacking structure located within the memory cell region, the cell stacking structure having at least a first insulating layer partially disposed in the substrate, a top surface of the first insulating layer being higher than a top surface of the substrate, and the top surface of the first insulating layer and a top surface of the first gate layer being on a same level.

公开(公告)号：US20180190664A1

公开(公告)日：2018-07-05

申请号：US15856022

申请日：2017-12-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chien-Cheng Tsai ,  Feng-Ming Huang ,  Ying-Chiao Wang ,  Chien-Ting Ho ,  Li-Wei Feng ,  Tsung-Ying Tsai

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L27/10894 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/3065 ,  H01L21/3081 ,  H01L27/10823 ,  H01L27/10876

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first buried gate and a second buried gate in the substrate on the memory region; forming a first silicon layer on the substrate on the periphery region; forming a stacked layer on the first silicon layer; forming an epitaxial layer on the substrate between the first buried gate and the second buried gate; and forming a second silicon layer on the epitaxial layer on the memory region and the stacked layer on the periphery region.

公开(公告)号：US09985035B1

公开(公告)日：2018-05-29

申请号：US15820455

申请日：2017-11-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Chien-Ting Ho ,  Yu-Cheng Tung

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10885 ,  H01L27/10808 ,  H01L27/10814 ,  H01L27/1085 ,  H01L27/10855 ,  H01L27/10894 ,  H01L27/10897

Abstract: A semiconductor memory structure includes a substrate including a memory cell region and a cell edge region adjacent to the memory cell region. Active regions are formed in the substrate and in the memory cell region and the cell edge region. At least a dummy bit line is formed on the active regions in the cell edge region. The dummy bit line extends along a first direction and overlaps at least two active regions along a second direction. The dummy bit line further includes a first inner line portion and an outer line portion. The first inner line portion and the outer line portion extend along the first direction and a width of the first inner line portion is different from a width of the outer line portion.

公开(公告)号：US09929162B1

公开(公告)日：2018-03-27

申请号：US15456564

申请日：2017-03-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Ying-Chiao Wang ,  Yu-Chieh Lin ,  Chien-Ting Ho

IPC: H01L27/10 ,  H01L27/108

CPC classification number: H01L27/10855 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

Abstract: A semiconductor device include a substrate including at least a memory cell region formed thereon, an isolation mesh formed on the substrate; and a plurality of storage node contact plugs. The semiconductor device includes a plurality of memory cells formed in the memory cell region. The isolation mesh includes a plurality of essentially homogeneous dielectric sidewalls and a plurality of first apertures defined by the dielectric sidewalls. The storage node contact plugs are respectively formed in the first apertures, and electrically connected to the memory cells respectively.

公开(公告)号：US09859283B1

公开(公告)日：2018-01-02

申请号：US15479290

申请日：2017-04-05

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Chien-Ting Ho ,  Yu-Cheng Tung

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10885 ,  H01L27/10808 ,  H01L27/10814 ,  H01L27/1085 ,  H01L27/10855 ,  H01L27/10894 ,  H01L27/10897

Abstract: A semiconductor memory structure includes a substrate including a memory cell region, a peripheral circuit region and a cell edge region defined thereon, and the cell edge region is defined in between the memory cell region and the peripheral circuit region. The semiconductor memory structure includes a plurality of active regions formed in the memory cell region, the cell edge region and the peripheral circuit region, and at least a dummy bit line formed on the active regions in the cell edge region. The dummy bit line is extended along a first direction and overlaps at least two active regions in a second direction. And the first direction and the second direction are perpendicular to each other. The dummy bit line includes a first inner line portion and an outer line portion, and the first inner line portion and the outer line portion include different widths and different spacers.