公开(公告)号：US20080059767A1

公开(公告)日：2008-03-06

申请号：US11842077

申请日：2007-10-29

Applicant: Craig Hansen ,  John Moussouris

Inventor： Craig Hansen ,  John Moussouris

IPC: G06F9/302 ,  G06F15/76

CPC classification number: G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3873 ,  G06F9/3885 ,  G06F15/7832

Abstract: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on multiple data elements stored registers in a register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results, wherein the execution unit is capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions.

Abstract translation: 提出了一种系统和装置，其涉及包括执行单元的可编程处理器，该执行单元可操作以解码和执行从指令路径接收的指令，并将存储在寄存器堆中的寄存器中的数据分割成多个数据元素，该执行单元能够执行多个 不同的组浮点和组整数算术运算，每个算术运算在寄存器文件中的多个数据元素存储的寄存器上产生返回到寄存器文件中的寄存器的连接结果，其中，连接结果包括多个单独的结果 其中，所述执行单元能够执行响应于数据处理指令以不同方式重新布置数据元素的组数据处理操作。

公开(公告)号：US20040205323A1

公开(公告)日：2004-10-14

申请号：US10757524

申请日：2004-01-15

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： Craig Hansen ,  John Moussouris

IPC: G06F009/44

CPC classification number: G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3873 ,  G06F9/3885 ,  G06F15/7832

Abstract: A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying a data selection operand and a first and a second register providing a plurality of data elements, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result.

Abstract translation: 一种可编程处理器和方法，用于通过结合执行单元来提高处理器的性能，所述执行单元可操作以解码和执行指定数据选择操作数的单个指令，以及提供多个数据元素的第一和第二寄存器，所述数据选择操作数包括多个 每个字段选择多个数据元素中的一个，所述执行单元可操作以将由数据选择操作数的每个字段选择的数据元素提供到预期结果的预定位置。

公开(公告)号：US20040156248A1

公开(公告)日：2004-08-12

申请号：US10716561

申请日：2003-11-20

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： Craig Hansen ,  John Moussouris

IPC: G11C007/00

CPC classification number: G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3873 ,  G06F9/3885 ,  G06F15/7832

Abstract: A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions in an instruction set comprising (a) group instructions that operate on a plurality of data elements in partitioned fields of a register to produce a catenated result, (b) aligned memory operations that move data between memory and register where the memory operand is aligned, and (c) unaligned memory operations where the memory operand is unaligned.

Abstract translation: 一种可编程处理器和方法，用于通过结合执行单元来操作以解码和执行指令集中的单个指令来提高处理器的性能，所述指令集包括：（a）对寄存器的分割字段中的多个数据元素进行操作的组指令， 连接结果，（b）对齐的存储器操作，其在存储器和寄存器之间移动数据，存储器操作数对齐，以及（c）存储器操作数未对齐的未对齐的存储器操作。

公开(公告)号：US20040049663A1

公开(公告)日：2004-03-11

申请号：US10436340

申请日：2003-05-13

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： Craig Hansen ,  John Moussouris

IPC: G06F009/00

CPC classification number: G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3873 ,  G06F9/3885 ,  G06F15/7832

Abstract: The present invention provides a system and method for expanding at least one source operand to a width greater than the width of either the general purpose register or the data path width. Operands are provided which are substantially larger than the data path width of the processor. A general purpose register is used to specify a memory address from which at least more than one, but typically several data path widths of data can be read. The data path functional unit is augmented with dedicated storage to which the memory operand is copied on an initial execution of the instruction. Further execution of the instruction or other similar instructions that specify the same memory address can read the dedicated storage to obtain the operand value. However, such reads are subject to conditions to verify that the memory operand has not been altered by intervening instructions. If the memory operand remains current, the memory operand fetch can be combined with one or more register operands in the functional unit, producing a result. The size of the result is, typically, constrained to that of a general register so that no dedicated or other special storage is required for the result.

Abstract translation: 本发明提供一种用于将至少一个源操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度的系统和方法。 提供了比处理器的数据路径宽度大得多的操作数。 通用寄存器用于指定至少可以读取数据的数据路径宽度至少多于一个的存储器地址。 在指令的初始执行时，数据路径功能单元用专用存储器进行扩充，存储器操作数被复制到该存储器操作数。 指定相同存储器地址的指令或其他类似指令的进一步执行可以读取专用存储器以获得操作数值。 然而，这样的读取受到条件的限制，以验证内存操作数没有被干预指令改变。 如果存储器操作数保持当前，则存储器操作数获取可以与功能单元中的一个或多个寄存器操作数组合，产生结果。 结果的大小通常限制为通用寄存器的大小，因此不需要专用或其他特殊存储。

公开(公告)号：US5819117A

公开(公告)日：1998-10-06

申请号：US541419

申请日：1995-10-10

Applicant: Craig C. Hansen

Inventor： Craig C. Hansen

IPC: G06F7/76 ,  G06F9/30 ,  G06F9/312 ,  G06F9/315 ,  G06F9/34 ,  G06F13/40 ,  G06F7/00

CPC classification number: G06F7/768 ,  G06F13/4013 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/34

Abstract: A method and data processing system for transferring data between the system and a memory system using more than one byte ordering convention by incorporating byte order information into instruction codes. The byte order information is coupled to a control unit along with other information characterizing the data transfer operation. In response to the byte order information and the data transfer operation information, the control unit generates a control signal that is coupled to a BPU. The control signal causes the BPU to rearrange the order of bytes in the data being transferred when the byte order information indicates a first byte ordering format. When the byte order information indicates a second byte ordering format, the BPU does not change the order of the bytes in the data being transferred.

Abstract translation: 一种方法和数据处理系统，用于通过将字节顺序信息并入指令代码中，使用多于一个字节排序的方式在系统和存储器系统之间传送数据。 字节顺序信息与表征数据传送操作的其他信息一起耦合到控制单元。 响应于字节顺序信息和数据传送操作信息，控制单元产生耦合到BPU的控制信号。 当字节顺序信息指示第一字节排序格式时，控制信号使BPU重新排列正在传送的数据中的字节顺序。 当字节顺序信息指示第二字节排序格式时，BPU不改变正在传送的数据中的字节顺序。

公开(公告)号：US5764084A

公开(公告)日：1998-06-09

申请号：US819179

申请日：1997-03-17

Applicant: Lavi A. Lev

Inventor： Lavi A. Lev

IPC: H03K19/00 ,  H03K19/017 ,  H03K19/096 ,  H03K19/173 ,  H01L25/00

CPC classification number: H03K19/01728 ,  H03K19/0013 ,  H03K19/0963 ,  H03K19/1738 ,  H01L2924/0002

Abstract: A robust family of pre-conditioned complementary CMOS logic elements using scaled MOSFETs and a single clock phase which may be easily interconnected to form high speed logic networks. The family includes both N-type and P-type pre-conditioned logic elements using a skewed complementary CMOS structure to achieve low power and high speed. The logic elements achieve next generation CMOS performance yet are manufactured using present day processes and equipment. Logic element implementation is described in detail. A method for scaling the MOSFETs according to the present invention is provided, and several routing methods for reducing interconnection cross-talk are set forth.

Abstract translation: 一个强大的预调制互补CMOS逻辑元件系列，使用缩放MOSFET和单个时钟相位，可以轻松地互连以形成高速逻辑网络。 该系列包括使用偏斜互补CMOS结构的N型和P型预调节逻辑元件，以实现低功率和高速度。 逻辑元件实现了下一代CMOS性能，而且是使用当今的工艺和设备制造的。 详细描述逻辑元件实现。 提供了根据本发明的用于缩放MOSFET的方法，并且阐述了用于减少互连串扰的几种布线方法。

公开(公告)号：US5707765A

公开(公告)日：1998-01-13

申请号：US654459

申请日：1996-05-28

Applicant: J. Fung Chen

Inventor： J. Fung Chen

IPC: H01L21/027 ,  G03F1/00 ,  G03F1/36 ,  G03F7/20 ,  G03F9/00

CPC classification number: G03F1/36 ,  G03F7/70433

Abstract: There is disclosed a photolithography mask and method of making the same that utilizes serifs to increase the correspondence between an actual circuit design and the final circuit pattern on a semiconductor wafer. The mask uses a plurality of serifs having a size determined by a resolution limit of the optical exposure tool used during the fabrication process. The serifs are positioned on the corner regions of the mask such that a portion of surface area for each of the serifs overlaps the corner regions of the mask. The size of the serifs is about one-third the resolution limit of said optical exposure tool. About 33 to about 40 percent of the total surface area of the serifs overlap the corner regions of the mask.

Abstract translation: 公开了一种光刻掩模及其制造方法，其利用衬线来增加半导体晶片上的实际电路设计和最终电路图案之间的对应关系。 掩模使用多个衬线，其具有由在制造过程中使用的光学曝光工具的分辨率极限确定的尺寸。 衬线位于掩模的拐角区域上，使得每个衬线的表面积的一部分与掩模的拐角区域重叠。 衬线的尺寸约为所述光学曝光工具的分辨率极限的三分之一。 衬线的总表面积的约33％至约40％与掩模的拐角区域重叠。

公开(公告)号：US5612638A

公开(公告)日：1997-03-18

申请号：US292799

申请日：1994-08-17

Applicant: Lavi A. Lev

Inventor： Lavi A. Lev

IPC: H03K19/00 ,  H03K19/017 ,  H03K19/096 ,  H03K19/173 ,  H03K19/094

CPC classification number: H03K19/01728 ,  H03K19/0013 ,  H03K19/0963 ,  H03K19/1738 ,  H01L2924/0002

Abstract: A robust family of pre-conditioned complementary CMOS logic elements using scaled MOSFETs and a single clock phase which may be easily interconnected to form high speed logic networks. The family includes both N-type and P-type pre-conditioned logic elements using a skewed complementary CMOS structure to achieve low power and high speed. The logic elements achieve next generation CMOS performance yet are manufactured using present day processes and equipment. Logic element implementation is described in detail. A method for scaling the MOSFETs according to the present invention is provided, and several routing methods for reducing interconnection cross-talk are set forth.

Abstract translation: 一个强大的预调制互补CMOS逻辑元件系列，使用缩放MOSFET和单个时钟相位，可以轻松地互连以形成高速逻辑网络。 该系列包括使用偏斜互补CMOS结构的N型和P型预调节逻辑元件，以实现低功率和高速度。 逻辑元件实现了下一代CMOS性能，而且是使用当今的工艺和设备制造的。 详细描述逻辑元件实现。 提供了根据本发明的用于缩放MOSFET的方法，并且阐述了用于减少互连串扰的几种布线方法。

公开(公告)号：US5541867A

公开(公告)日：1996-07-30

申请号：US377424

申请日：1995-01-24

Applicant: Alan G. Corry ,  Manoj Puri ,  Robert A. Sutherland

Inventor： Alan G. Corry ,  Manoj Puri ,  Robert A. Sutherland

IPC: G06F17/00 ,  G06F17/15

CPC classification number: G06K9/0057 ,  G06K9/0051

Abstract: An apparatus and method for decorrelating pairs of mutually contaminated channels in a multi-channel digital signal including two identical data processing paths and a feedback path. Each pair of mutually contaminated channels consists of a first contaminated channel and a second contaminated channel. Initially, first and second shined signals are generated by shifting the original contaminated signal such that the first shined signal has the first contaminated channel centered at zero frequency and the second shined signal has the second contaminated channel centered at zero frequency. Each of the first and second shifted signals are coupled to one of the two identical signal processing paths. The first path generates an error corruption component corresponding to the first shifted input signal and subtracts this corruption component from the second shifted signal in order to generate a third decorrelated digital signal. The second path generates an error corruption component corresponding to the second shined input signal and subtracts it from the first shifted signal in order to generate a fourth decorrelated digital signal. The feedback path generates a current average error correlation factor by multiplying the third and fourth to generate an instantaneous error factor and summing this with the previous average error correlation factor for all samples. The current average error correlation factor is used to generate the first and second error corruption components. Each of the corrupted channels in the original contaminated digital signal are decorrelated when the third and rough digital signals are decorrelated.

Abstract translation: 一种用于在包括两个相同的数据处理路径和反馈路径的多通道数字信号中去相互关联相互污染的通道的装置和方法。 每对相互污染的通道由第一污染通道和第二污染通道组成。 最初，通过移动原始污染信号来产生第一和第二发光信号，使得第一发光信号具有以零频率为中心的第一污染通道，而第二发光信号具有以零频率为中心的第二污染通道。 第一和第二移位信号中的每一个耦合到两个相同的信号处理路径之一。 第一路径产生与第一移位输入信号对应的错误损坏部件，并从第二移位信号中减去该损坏部件，以产生第三去相关数字信号。 第二路径产生与第二发光输入信号相对应的误差损坏分量，并从第一移位信号中减去它，以产生第四解相关数字信号。 反馈路径通过乘以第三和第四来产生当前平均误差相关因子以产生瞬时误差因子，并将其与所有样本的先前平均误差相关因子相加。 当前的平均误差相关因子用于产生第一和第二错误损坏组件。 当第三和粗略的数字信号被去相关时，原始受污染的数字信号中的每个被破坏的信道都被去相关。

公开(公告)号：US5283479A

公开(公告)日：1994-02-01

申请号：US842922

申请日：1992-02-27

Applicant: Geert Rosseel ,  Bill Herndon ,  James A. Matthews

Inventor： Geert Rosseel ,  Bill Herndon ,  James A. Matthews

IPC: H03K19/003 ,  H03K17/14 ,  H03K17/567 ,  H03K17/60 ,  H03K19/08 ,  H03K19/086 ,  H03K19/0944 ,  H03K17/16

CPC classification number: H03K19/086 ,  H03K17/14 ,  H03K17/567 ,  H03K17/603 ,  H03K19/09448

Abstract: An improved BiCMOS logic circuit utilizes an emitter-coupled pair of bipolar transistors for differentially comparing an input signal with a logic reference level. Each of the bipolar transistors are resistively loaded by a network of p-channel metal-oxide-semiconductor (PMOS) transistors coupled in parallel. At least one of the parallel combination of transistors has its gate coupled to a control signal providing a variable load resistance. The control signal is preferably provided by a feedback network which maintains a constant voltage swing across the network over temperature.

Abstract translation: 改进的BiCMOS逻辑电路利用发射极耦合的双极晶体管对将输入信号与逻辑参考电平进行差分比较。 每个双极晶体管由并联耦合的p沟道金属氧化物半导体（PMOS）晶体管的网络电​​阻加载。 晶体管的并联组合中的至少一个具有耦合到提供可变负载电阻的控制信号的栅极。 控制信号优选由反馈网络提供，该网络通过温度在网络上保持恒定的电压摆幅。