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61.发明申请公开(公告)号：US20180131338A1
公开(公告)日：2018-05-10
申请号：US15725814
申请日：2017-10-05
Applicant: FUJITSU LIMITED
Inventor： Toshihiro Shimura
IPC: H03H7/24 , H03G1/00 , G01R31/02 , H01P1/18 , H01P1/15 , H01P1/22 , H03H7/20 , G01R31/319 , H04L27/22
CPC classification number: H03G1/007 , G01R31/025 , G01R31/31926 , H01P1/15 , H01P1/18 , H01P1/22 , H03G1/0088 , H03G2201/106 , H03H7/20 , H03H11/20 , H03H11/245 , H04L27/22
Abstract: A variable attenuation device includes: a first variable attenuator configured to receive a first signal through a first input end, attenuate the first signal by an amount of attenuation according to a control voltage, and output the attenuated first signal through a first output end, the first signal being one of a pair of differential signals having a 180-degree phase difference; a second variable attenuator configured to receive a second signal through a second input end, attenuate the second signal by the amount of attenuation according to the control voltage, and output the attenuated second signal through a second output end, the second signal being the other one of the pair of differential signals; a first signal distributer configured to distribute the second signal to the first output end; and a second signal distributer configured to distribute the first signal to the second output end.
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公开(公告)号：US20180083579A1
公开(公告)日：2018-03-22
申请号：US15272103
申请日：2016-09-21
Applicant: Peregrine Semiconductor Corporation
Inventor： Hossein Noori , Chih-Chieh Cheng
CPC classification number: H03F1/3205 , H03F1/56 , H03F3/195 , H03F3/72 , H03F2200/18 , H03F2200/21 , H03F2200/211 , H03F2200/213 , H03F2200/222 , H03F2200/225 , H03F2200/24 , H03F2200/243 , H03F2200/249 , H03F2200/27 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/312 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/417 , H03F2200/451 , H03F2200/48 , H03F2200/489 , H03F2200/492 , H03F2200/495 , H03F2200/546 , H03F2200/72 , H03F2200/75 , H03G1/0029 , H03G1/0088 , H03G1/0094 , H03G3/001 , H03G3/008 , H03G3/10 , H03G2201/106 , H03G2201/307 , H03G2201/504
Abstract: A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” input stage and a “common gate” output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.
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公开(公告)号：US20180062621A1
公开(公告)日：2018-03-01
申请号：US15687475
申请日：2017-08-26
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Yan YAN , Junhyung LEE
CPC classification number: H03H11/245 , H03F1/0277 , H03F3/19 , H03F3/195 , H03F3/211 , H03F3/72 , H03F2200/294 , H03F2200/451 , H03F2203/7215 , H03F2203/7221 , H03G1/0029 , H03G1/0088 , H03G3/3042 , H03G3/3063 , H03G2201/106 , H03H7/25 , H04B1/40
Abstract: Attenuators having phase shift and gain compensation circuits. In some embodiments, a radio-frequency (RF) attenuator circuit can include one or more attenuation blocks arranged in series between an input node and an output node, with each attenuation block including a local bypass path. The RF attenuator circuit can further include a global bypass path implemented between the input node and the output node. The RF attenuator circuit can further include a phase compensation circuit configured to compensate for an off-capacitance effect associated with at least one of the global bypass path and the one or more local bypass paths.
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公开(公告)号：US20180062600A1
公开(公告)日：2018-03-01
申请号：US15690762
申请日：2017-08-30
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Junhyung LEE , Rimal Deep Singh , Johannes Jacobus Emile Maria Hageraats , Joshua Haeseok Cho , Bipul Agarwal , Aravind Kumar Padyana
CPC classification number: H03G3/3042 , H03F1/223 , H03F1/56 , H03F3/193 , H03F2200/211 , H03F2200/222 , H03F2200/387 , H03F2200/451 , H03G1/0029 , H03G1/0088 , H03G3/001 , H03G3/3063 , H03G2201/106 , H04B7/08 , H04B7/0842
Abstract: Described herein are variable gain amplifiers and multiplexers that embed programmable attenuators into switchable paths that allow signals in a high gain mode to bypass attenuation. This advantageously reduces or eliminates performance penalties in the high gain mode. The programmable attenuators can be configured to improve linearity of the amplification process through pre-LNA attenuation in targeted gain modes. In addition, described herein are variable gain amplifiers with embedded attenuators in a switching network. The attenuators can be embedded onto switches and can be configured to have little or no effect on a noise factor in a high gain mode because the switching network can provide an attenuation bypass in a high gain mode and an attenuation in other gain modes. The programmable attenuators can be embedded onto a multi-input LNA architecture.
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Patent Agency Ranking
公开(公告)号：US20170338774A1
公开(公告)日：2017-11-23
申请号：US15527361
申请日：2015-11-19
Applicant: SONY CORPORATION
Inventor： KATSUAKI TAKAHASHI , HIDEYUKI TAKANO , NAOTO YOSHIKAWA
CPC classification number: H03F1/26 , H03F1/223 , H03F3/193 , H03F3/211 , H03F3/3022 , H03F3/68 , H03F2200/294 , H03F2200/372 , H03F2200/451 , H03G1/0088 , H03G1/0094 , H03G2201/106
Abstract: An output signal can be free of any noise component generated from an amplifier disposed in a path, without degradation of the S/N ratio of the output signal. An amplifier includes: a first amplifier that is connected to an input node and generates a first intermediate signal; a feedback resistor that enables feedback of the first intermediate signal to the input node; an attenuator that receives the first intermediate signal and generates a second intermediate signal; a second amplifier that is connected to the input node and generates a third intermediate signal; a third amplifier that is connected to the input node and generates a fourth intermediate signal; and an adder that generates an output signal, using the second intermediate signal, the third intermediate signal, and the fourth intermediate signal.
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公开(公告)号：US09755579B1
公开(公告)日：2017-09-05
申请号：US15374803
申请日：2016-12-09
Applicant: NXP USA INC.
Inventor： Abdulrhman M. S. Ahmed , Joseph Staudinger
CPC classification number: H03F1/0288 , H01C1/16 , H03F1/0266 , H03F1/3241 , H03F1/3282 , H03F3/193 , H03F3/245 , H03F2200/102 , H03F2200/18 , H03F2200/451 , H03G3/3042 , H03G2201/106 , H04L25/03834 , H04L27/22
Abstract: The embodiments described herein include amplifiers configured for use in radio frequency (RF) applications. In accordance with these embodiments, the amplifiers are implemented to generate a shaped envelope signal, and to apply the shaped envelope signal to transistor gate(s) of the amplifier to provide gate bias modulation. So configured, the shaped envelope signal may facilitate high linearity in the amplifier.
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公开(公告)号：US09723405B2
公开(公告)日：2017-08-01
申请号：US15246373
申请日：2016-08-24
Applicant: Red Lion 49 Limited
Inventor： David Joseph Mate
CPC classification number: H04R3/04 , H03F3/187 , H03F3/45071 , H03F3/45475 , H03F2200/03 , H03F2200/165 , H03F2200/321 , H03F2203/45576 , H03F2203/45614 , H03G1/0005 , H03G1/0088 , H03G2201/106 , H03H11/245
Abstract: Apparatus (301) for switchable attenuation of a differential input signal from a microphone includes positive and negative non-attenuating paths (406, 410) have n- and p-type MOSFETs (421, 422, 423, 424) in back-to-back configurations; positive and negative attenuating paths (405, 409) have n- and p-type MOSFETs (415, 416, 418, 419) in back-to-back configurations in combination with resistors; a gate driver (425) applies a drive signal of one polarity (QNEG) to gates of the n-type MOSFETs in the attenuating paths and the p-type MOSFETs in the non-attenuating paths, and a drive signal of opposite polarity (QPOS) to the gates of the p-type MOSFETs in the attenuating paths and the n-type MOSFETs in the non-attenuating paths; and the state of the MOSFETs depends on the drive signals at their gates, and thus the input signal may be routed via either the non-attenuating paths or the attenuating paths by controlling the drive signals.
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公开(公告)号：US20170163229A1
公开(公告)日：2017-06-08
申请号：US15365092
申请日：2016-11-30
Applicant: MURATA MANUFACTURING CO., LTD.
Inventor： Yasushi OYAMA , Takayuki TSUTSUI , Kazuhito NAKAI
CPC classification number: H03G1/0094 , H03F1/56 , H03F3/19 , H03F3/213 , H03F3/245 , H03F3/72 , H03F2200/111 , H03F2200/165 , H03F2200/222 , H03F2200/318 , H03F2200/387 , H03F2203/7209 , H03G2201/106 , H03G2201/40
Abstract: A power amplification module includes a first input terminal that receives a first transmit signal in a first frequency band, a second input terminal that receives a second transmit signal in a second frequency band having a narrower transmit/receive frequency interval than the first frequency band, a first amplification circuit that receives and amplifies the first transmit signal to produce a first amplified signal and outputs the first amplified signal, a second amplification circuit that receives and amplifies the second transmit signal to produce a second amplified signal and outputs the second amplified signal, a third amplification circuit that receives and amplifies the first or second amplified signal to produce an output signal and outputs the output signal, and an attenuation circuit located between the second input terminal and the second amplification circuit and configured to attenuate a receive frequency band component of the second frequency band.
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公开(公告)号：US20130314143A1
公开(公告)日：2013-11-28
申请号：US13959254
申请日：2013-08-05
Applicant: FREESCALE SEMICONDUCTOR, INC.
Inventor： ABDULRHMAN M.S. AHMED , MARIO M. BOKATIUS , PAUL R. HART , JOSEPH STAUDINGER , RICHARD E. SWEENEY
IPC: G06G7/10
CPC classification number: H03F1/0288 , G06F13/4282 , G06G7/10 , H03F3/189 , H03F3/19 , H03F3/211 , H03F3/602 , H03F3/68 , H03F2200/387 , H03F2200/438 , H03F2200/451 , H03F2203/21106 , H03F2203/21193 , H03G1/0088 , H03G2201/106 , H04L7/0079 , H04L27/22
Abstract: An adjustable power splitter includes: a power divider with an input and a first and second divider output; a first adjustable phase shifter and first adjustable attenuator series coupled to the first divider output and providing a first power output; a second adjustable phase shifter and second adjustable attenuator series coupled to the second divider output and providing a second power output; an interface; and a controller. The controller is configured to receive, via the interface, data indicating phase shifts to be applied by the first and second adjustable phase shifters and attenuation levels to be applied by the first and second adjustable attenuators, and to control, based on the data, the phase shifts and attenuation levels applied by the first and second adjustable phase shifters and the first and second adjustable attenuators.
Abstract translation: 可调功率分配器包括：具有输入的功率分配器和第一和第二分频器输出; 第一可调移相器和第一可调衰减器串联耦合到第一分频器输出并提供第一功率输出; 第二可调移相器和第二可调衰减器串联耦合到第二分频器输出并提供第二功率输出; 界面; 和控制器。 控制器被配置为经由接口接收指示要由第一和第二可调移相器施加的相移的数据和由第一和第二可调衰减器施加的衰减电平，并且基于该数据来控制 由第一和第二可调移相器以及第一和第二可调衰减器施加的相移和衰减电平。
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