公开(公告)号：US4285780A

公开(公告)日：1981-08-25

申请号：US957291

申请日：1978-11-02

Applicant: Herbert I. Schachter

Inventor： Herbert I. Schachter

IPC: H05K3/00 ,  H05K3/10 ,  H05K3/18 ,  H05K3/28 ,  H05K3/42 ,  H05K3/46 ,  C25D5/02

CPC classification number: H05K3/429 ,  H05K3/423 ,  H05K3/4602 ,  H05K2201/091 ,  H05K2201/092 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2203/0733 ,  H05K3/0023 ,  H05K3/108 ,  H05K3/181 ,  H05K3/28 ,  H05K3/428 ,  Y10T29/49126

Abstract: A multi-level printed circuit board with at least two levels of circuitry. A substrate has a first level of circuitry, an insulating covering or layer over the entire surface of the substrate and the circuitry except in first predetermined areas, a second level of circuitry is formed over said insulating covering or layer and metallurgically bonded to form electrically conductive joints at the predetermined uncovered areas with the first level of circuitry.The method of making a multi-level printed circuit board comprises the steps of forming at least one level of circuitry on at least one side of a substrate, applying an insulating covering or layer over the entire surface of the substrate and circuitry except in a first number of predetermined areas, forming a thin adherent conductive coating over all exposed surfaces, applying a temporary mask over the conductive coating except in second predetermined areas which define the second level of circuitry on the side of said substrate, forming copper circuitry in said second predetermined areas, and removing the temporary mask and said adherent conductive coating. The formation of the second level of circuitry is repeated for as many levels as is desired, and levels of circuitry may be formed on both sides of the substrate. A final level of circuitry is formed and is covered by a final insulating coating except in final predetermined areas.

Abstract translation: 具有至少两级电路的多级印刷电路板。 衬底在衬底的整个表面上具有第一级电路，绝缘覆盖物或层，除了在第一预定区域之外，电路的第二级电路形成在所述绝缘覆盖物或层上并且冶金结合以形成导电 在具有第一级电路的预定未覆盖区域处的接头。 制造多级印刷电路板的方法包括以下步骤：在衬底的至少一侧上形成至少一层电路，在衬底和电路的整个表面上施加绝缘覆盖物或层，除了第一 预定面积的数量，在所有暴露的表面上形成薄的粘附导电涂层，在导电涂层上施加临时掩模，除了限定所述衬底侧面上的第二级别的电路的第二预定区域之外，在所述第二预定区域中形成铜电路 区域，并且去除临时掩模和所述粘附导电涂层。 重复第二级电路的形成，以达到期望的许多电平，并且电路的电平可以形成在衬底的两侧上。 形成最终级别的电路，并且由最终的绝缘涂层覆盖，除了最终的预定区域之外。