公开(公告)号：US5666501A

公开(公告)日：1997-09-09

申请号：US413315

申请日：1995-03-30

Applicant: Timothy Leonard Jones ,  Paula Jean Moreland

Inventor： Timothy Leonard Jones ,  Paula Jean Moreland

IPC: G06F9/445 ,  G06F15/00 ,  G06F12/00 ,  H01J13/00

CPC classification number: G06F8/61

Abstract: A computer-implemented method, apparatus, memory embodying computer-readable code for installing software stored on a second machine to a first machine in a distributed computing network is provided. The first machine includes at least a display, processor, and user controls. The method includes the steps of displaying available, installable source objects of a second machine embodying software that is installable on a first machine, displaying software bundle objects having software items, wherein at least one software item is in common with one of the software items in the selected source object in response to a selection by user controls of at least one source object, and installing on the first machine an intersection of the first software items and the second software items.

Abstract translation: 提供了一种计算机实现的方法，装置，体现用于将存储在第二机器上的软件安装到分布式计算网络中的第一机器的计算机可读代码。 第一台机器至少包括一个显示器，处理器和用户控件。 该方法包括以下步骤：显示体现可在第一机器上安装的软件的第二机器的可供安装的源对象，显示具有软件项目的软件束对象，其中至少一个软件项目与 所述选择的源对象响应于用户对至少一个源对象的控制的选择，并且在所述第一机器上安装所述第一软件项和所述第二软件项的交集。

公开(公告)号：US5604873A

公开(公告)日：1997-02-18

申请号：US366230

申请日：1994-12-28

Applicant: Robert J. Fite ,  David A. Underwood ,  Dale Rembold

Inventor： Robert J. Fite ,  David A. Underwood ,  Dale Rembold

IPC: G06F13/40 ,  H01J13/00

CPC classification number: G06F13/4081

Abstract: A disk drive controller having a plurality of disk drive interfaces, each interface includes a connector, a delay circuit, and a set of power application circuits is provided to a server to support hot docking of SCA drives. Each connector is adapted to mate with a hot docking disk drive having equal length connecting pins, and detect the presence of such disk drive when the hot docking disk drive makes contact with the connector. Each delay circuit generates a set of properly delayed enabling signals to the corresponding power application circuits. Each set of power application circuits regulates power applications to the hot docking disk drive making contact with the corresponding connector. The delayed and regulated manner of applying power prevents voltage and power swings that might disrupt on-going operations and/or cause damages to the neighboring drives.

Abstract translation: 具有多个磁盘驱动器接口的磁盘驱动器控制器，每个接口包括连接器，延迟电路和一组电源应用电路，以提供给服务器以支持SCA驱动器的热对接。 每个连接器适于与具有相等长度的连接销的热对接盘驱动器配合，并且当热对接盘驱动器与连接器接触时，检测这种磁盘驱动器的存在。 每个延迟电路产生一组适当延迟的使能信号给相应的电源应用电路。 每组电力应用电路将电力应用调节到与对应连接器接触的热对接磁盘驱动器。 施加功率的延迟和调节方式可防止可能中断正在进行的操作的电压和功率摆动和/或对相邻驱动器造成损害。

公开(公告)号：US5600650A

公开(公告)日：1997-02-04

申请号：US499728

申请日：1995-07-07

Applicant: Rasoul M. Oskouy

Inventor： Rasoul M. Oskouy

IPC: G06F1/12 ,  H04L7/00 ,  H04L12/56 ,  H04Q3/00 ,  H04Q11/04 ,  H01J13/00 ,  H04J3/06

CPC classification number: H04Q11/0478 ,  H04L12/5601 ,  H04L2012/5674

Abstract: An asynchronous transfer mode (ATM) segmentation and reassembly (SAR) chip is provided for interfacing a host computer with an ATM system having a physical layer (PHY) chip incorporating, for example, a Unified Test and Operations Physical Interface for ATM (UTOPIA) protocol. The PHY chip is capable of operating at both 155 Mbps and 622 Mbps data transmission rates. The UTOPIA protocol requires a clock which is provided by the SAR chip. In an exemplary embodiment described herein, the SAR chip is configured to accommodate both data transmission rates and to synthesize appropriate clock signals for driving the PHY chip which facilitate the clocking out of data and the sampling of data.

Abstract translation: 提供了异步传输模式（ATM）分段和重组（SAR）芯片，用于将主计算机与具有结合例如用于ATM（UTOPIA）的统一测试和操作物理接口的物理层（PHY） 协议。 PHY芯片能够以155 Mbps和622 Mbps的数据传输速率工作。 UTOPIA协议需要由SAR芯片提供的时钟。 在这里描述的示例性实施例中，SAR芯片被配置为适应数据传输速率并且合成用于驱动PHY芯片的适当的时钟信号，这有助于数据的计时和数据采样。

公开(公告)号：US5581710A

公开(公告)日：1996-12-03

申请号：US554800

申请日：1995-11-07

Applicant: Francis E. Noel, Jr. ,  Kenneth D. Schultz ,  Thomas E. Stammely

Inventor： Francis E. Noel, Jr. ,  Kenneth D. Schultz ,  Thomas E. Stammely

IPC: H04L12/42 ,  H01J13/00

CPC classification number: H04L12/42

Abstract: A ring network of workstations interconnected on a single simplex ring is converted to duplex communications on the single ring by placing two transceivers in each workstation and adding a duplex conversion device between each workstation and its ring terminal box. One of the transceivers receives and retransmits signals in a clockwise direction around the ring; the other transceiver receives and retransmits signals in a counter-clockwise direction around the ring. The clockwise and counter-clockwise signals are superimposed on the ring but are isolated at the workstations by the duplex conversion device.

Abstract translation: 通过在每个工作站中放置两个收发器，并在每个工作站和其环形端子盒之间添加双工转换设备，将单个单环上互联的工作站的环网转换为单环的双工通信。 收发器之一接收并围绕环顺时针方向重发信号; 另一个收发器以围绕环的逆时针方向接收和重发信号。 顺时针和逆时针信号叠加在环上，但通过双工转换设备在工作站隔离。

公开(公告)号：US5579482A

公开(公告)日：1996-11-26

申请号：US506754

申请日：1995-07-26

Applicant: Robert L. Einkauf ,  Glen M. Riley ,  James M. Von De Bur

Inventor： Robert L. Einkauf ,  Glen M. Riley ,  James M. Von De Bur

IPC: G05B19/418 ,  H02J13/00 ,  H04L12/28 ,  H04L29/06 ,  H04L29/08 ,  H01J13/00

CPC classification number: H04L12/28 ,  G05B19/41855 ,  H04L29/06 ,  H04L67/12 ,  H04L69/329

Abstract: An interface file structure for allowing transfer of information between nodes in a network and a binding process for configuring nodes in the network. The interface offers an advantageous format designed to provide for minimal reading and writing of records while requiring minimal storage space per record. Further, an advantageous format for storing numeric information is disclosed in which information providing the number of buffers allocated and the size of such buffers is stored in a single nibble thus reducing required storage space.

Abstract translation: 用于允许在网络中的节点之间传送信息的接口文件结构以及用于配置网络中的节点的绑定过程。 该界面提供了一种有利的格式，旨在提供最少的记录读取和写入，同时每个记录需要最少的存储空间。 此外，公开了用于存储数字信息的有利格式，其中提供分配的缓冲器数量和这种缓冲器的大小的信息被存储在单个半字节中，从而减少所需的存储空间。

公开(公告)号：US5577208A

公开(公告)日：1996-11-19

申请号：US902905

申请日：1992-06-23

Applicant: Patrice Couturier

Inventor： Patrice Couturier

IPC: H04L13/00 ,  H01J13/00

CPC classification number: H04L13/00

Abstract: A multimedia intercommunications installation suitable for conveying animated images between a plurality of users each provided with a microcomputer type of workstation. Each user is provided with a new central unit which processes the pixels for the screen directly. The new CPU receives and forwards data concerning animated images, sound, and writing. The writing data is advantageously generated by the writing members already provided for the workstation.

Abstract translation: 一种多媒体互通装置，适用于在各自提供有微型计算机类型的工作站的多个用户之间传送动画图像。 每个用户都设置有一个新的中央单元，用于直接处理屏幕的像素。 新CPU接收和转发有关动画图像，声音和写入的数据。 写入数据有利地由已经为工作站提供的写入构件生成。

公开(公告)号：US5530812A

公开(公告)日：1996-06-25

申请号：US246057

申请日：1994-05-19

Applicant: You Seong Kim ,  Sang Rae Lee

Inventor： You Seong Kim ,  Sang Rae Lee

IPC: G06F13/38 ,  G06F13/42 ,  H04L29/10 ,  H01J13/00

CPC classification number: G06F13/4213

Abstract: A bus interface circuit is for coupling between a microprocessor having an architecture in which address and data buses are separated and peripheral equipment having a multiplexing bus architecture. The bus interface circuit includes a first delay circuit for delaying a first address strobe signal of a microprocessor to obtain a first data strobe signal, a second delay circuit for delaying the first data strobe signal to obtain a second data strobe signal for the peripheral equipment, a logic circuit for multiplying an inverted first data strobe signal and the first address strobe signal to obtain a second address strobe signal for the peripheral equipment, a first buffer enabled by the first data strobe signal for transmitting address data of the microprocessor, and second buffer means enabled by the second address strobe signal for transmitting and receiving data information between the microprocessor and the peripheral equipment.

Abstract translation: 总线接口电路用于在具有地址和数据总线分离的架构的微处理器之间耦合以及具有复用总线结构的外围设备。 总线接口电路包括用于延迟微处理器的第一地址选通信号以获得第一数据选通信号的第一延迟电路，用于延迟第一数据选通信号以获得外围设备的第二数据选通信号的第二延迟电路， 逻辑电路，用于将反相的第一数据选通信号和第一地址选通信号相乘以获得用于外围设备的第二地址选通信号，由第一数据选通信号用于发送微处理器的地址数据的第一缓冲器和第二缓冲器 由第二地址选通信号启用的装置，用于在微处理器和外围设备之间发送和接收数据信息。

公开(公告)号：US5517627A

公开(公告)日：1996-05-14

申请号：US113417

申请日：1993-08-27

Applicant: Brian Petersen

Inventor： Brian Petersen

IPC: G06F5/00 ,  G06F13/28 ,  G06F13/40 ,  H01J13/00

CPC classification number: G06F13/28 ,  G06F13/4013 ,  G06F5/00

Abstract: A data aligner transfers data from an input having N+1 byte lanes to an output having N+1 byte lanes. The data aligner includes a write data aligner and a read data aligner. The write data aligner includes a write shifter coupled to the N input byte lanes and a stage having N selector/registers S1(i). The N selector/registers each have a queuing register R(i) and bypass multiplexer M(i). The N selector/registers are coupled to the N output byte lanes. The write shifter and N selector/registers S1(i) are coupled to a control circuit. The read data aligner includes a stage having N selector/registers S2(i) and a read shifter. The S2(i) selector/registers are coupled to N+1 byte input lanes with the S2(i) outputs coupled to the N read shifter inputs. The read shifter outputs are then coupled to the N+1 output byte lanes. Finally, a control circuit is coupled to the selector/registers S2(i) and read shifter.

Abstract translation: 数据对准器将数据从具有N + 1字节通道的输入传送到具有N + 1字节通道的输出。 数据对准器包括写数据对准器和读数据对准器。 写数据对准器包括耦合到N个输入字节通道的写移位器和具有N个选择器/寄存器S1（i）的级。 N个选择器/寄存器各具有排队寄存器R（i）和旁路复用器M（i）。 N个选择器/寄存器耦合到N个输出字节通道。 写移位器和N选择器/寄存器S1（i）耦合到控制电路。 读取数据对准器包括具有N个选择器/寄存器S2（i）和读取移位器的级。 S2（i）选择器/寄存器耦合到N + 1字节输入通道，S2（i）输出耦合到N个读取移位器输入。 读取移位器输出然后被耦合到N + 1个输出字节通道。 最后，控制电路耦合到选择器/寄存器S2（i）和读取移位器。

公开(公告)号：US5515508A

公开(公告)日：1996-05-07

申请号：US169345

申请日：1993-12-17

Applicant: Christopher E. Pettus ,  Donald R. Loomis ,  Christina E. Warren

Inventor： Christopher E. Pettus ,  Donald R. Loomis ,  Christina E. Warren

IPC: G06F9/46 ,  H04L29/06 ,  G06F13/00 ,  H01J13/00

CPC classification number: G06F9/547 ,  G06F9/465 ,  H04L29/06

Abstract: Novel object-oriented client-server facility (CSF) and networking service facility (NSF) interfaces implement communication between application programs residing in client and server nodes of a distributed services network. The CSF interface includes remote procedure call (RPC) objects for invoking and responding to service requests at the nodes, and application programming interface (API) objects for transporting those requests between the nodes. However, the API objects only provide communication transports within a node. Accordingly, the API and RPC objects interact with dynamically-configurable protocol stacks within the NSF interfaces to complete the transport mechanism needed by an application program on the client node when accessing services on a remote server node.

Abstract translation: 新型面向对象的客户端 - 服务器设备（CSF）和网络服务设施（NSF）接口实现驻留在分布式服务网络的客户机和服务器节点之间的应用程序之间的通信。 CSF接口包括用于调用和响应节点处的服务请求的远程过程调用（RPC）对象，以及用于在节点之间传送这些请求的应用程序编程接口（API）对象。 然而，API对象仅提供节点内的通信传输。 因此，API和RPC对象与NSF接口内的动态可配置协议栈进行交互，以便在访问远程服务器节点上的服务时完成客户端节点上的应用程序所需的传输机制。

公开(公告)号：US5513323A

公开(公告)日：1996-04-30

申请号：US715179

申请日：1991-06-14

Applicant: Marvin L. Williams ,  Roselyn H. Yun

Inventor： Marvin L. Williams ,  Roselyn H. Yun

IPC: G06F12/00 ,  G06F5/00 ,  G06F13/00 ,  G06F17/21 ,  G06F17/22 ,  G06F3/00 ,  H01J13/00

CPC classification number: G06F17/2282

Abstract: A method and apparatus for determining an optimal multistage transformation from a first document format to a second document format via multiple format type transformation applications. Each document format type within a data processing system is identified and associated with a node within a format type network. An expenditure cost associated with each format type transformation application, such as time cost or information loss cost, is identified and associated with a link between two associated nodes in the format type network. An optimal path from a first node within the format type network to a second node is then calculated by means of links having minimal expenditure cost associated therewith. In one depicted embodiment of the present invention an optimal path from a selected node to all other nodes within the format type network is calculated and utilized for all future desired transformations.

Abstract translation: 一种用于通过多格式类型变换应用来确定从第一文档格式到第二文档格式的最佳多阶段变换的方法和装置。 数据处理系统内的每个文档格式类型被识别并与格式类型网络内的节点相关联。 与每个格式类型转换应用相关联的支出成本（诸如时间成本或信息损失成本）被识别并且与格式类型网络中的两个关联节点之间的链路相关联。 然后，通过具有与其相关联的最小支出成本的链路来计算从格式类型网络中的第一节点到第二节点的最佳路径。 在本发明的一个所描绘的实施例中，计算并且利用从所选节点到格式类型网络内的所有其他节点的最佳路径用于所有未来的所需转换。