公开(公告)号：US20240395762A1

公开(公告)日：2024-11-28

申请号：US18201319

申请日：2023-05-24

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WU-DER YANG

IPC: H01L23/00

Abstract: A semiconductor device is provided, which includes a semiconductor die and a redistribution layer. The redistribution layer is formed on the semiconductor die, and includes a plurality of center pads, a plurality of edge pads, and a plurality of conductive wires electrically connecting the plurality of center pads to the plurality of edge pads. Each of the plurality of conductive wires comprises at least two turning points, and an inner angle at each turning point is greater than a predetermined angle.

公开(公告)号：US20240387165A1

公开(公告)日：2024-11-21

申请号：US18199455

申请日：2023-05-19

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： TSE-YAO HUANG

IPC: H01L21/02 ,  H01L21/033 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom interconnector layer positioned in the substrate; a bottom dielectric layer positioned on the bottom glue layer; an interconnector structure positioned along the bottom dielectric layer and the bottom glue layer, positioned on the bottom interconnector layer, and positioned on the bottom dielectric layer; a top glue layer conformally positioned on the bottom dielectric layer and the interconnector structure; a top dielectric layer positioned surrounding the top glue layer. A top surface of the top glue layer and a top surface of the top dielectric layer are substantially coplanar. The top dielectric layer is porous.

公开(公告)号：US12150290B2

公开(公告)日：2024-11-19

申请号：US17670758

申请日：2022-02-14

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Li-Han Lu

IPC: H10B12/00 ,  H01L29/08 ,  H01L29/16

Abstract: A semiconductor device includes a first source/drain region and a second source/drain region disposed in a semiconductor substrate. The semiconductor device also includes a word line structure disposed in the semiconductor substrate and between the first source/drain region and the second source/drain region. The word line structure includes a composite gate dielectric, and a lower electrode layer disposed over the composite gate dielectric. The word line structure also includes an upper electrode layer disposed over the lower electrode layer, and a graphene layer disposed between the lower electrode layer and the upper electrode layer. The composite gate dielectric includes a gate dielectric layer and a protection liner.

公开(公告)号：US12148791B2

公开(公告)日：2024-11-19

申请号：US18219247

申请日：2023-07-07

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Szu-Yu Hou ,  Li-Han Lin

IPC: H10B12/00 ,  H01L49/02

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate having a first surface, a plurality of layers disposed on the first surface of the substrate. The plurality of layers includes a first nitride layer disposed on the first surface of the substrate, a first silicon-containing layer disposed on the first nitride layer, an intermediate nitride layer disposed on the first silicon-containing layer, a second silicon-containing layer disposed on the intermediate nitride layer, and a second nitride layer disposed on the second silicon-containing layer. In addition, the semiconductor structure includes a trench capacitor penetrating the plurality of layers and in contact with the substrate. The trench capacitor has a first portion having a first lateral surface and a second portion having a second lateral surface, and the first lateral surface has a slope different from that of the second lateral surface.

公开(公告)号：US12148722B2

公开(公告)日：2024-11-19

申请号：US17747300

申请日：2022-05-18

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ming-Hung Hsieh

IPC: H01L23/00

Abstract: The present application discloses a semiconductor device with a barrier layer including aluminum fluoride and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a circuit layer positioned on the substrate, a pad layer positioned in the circuit layer and including aluminum and copper, a first barrier layer positioned on the pad layer and including aluminum fluoride, and a first connector positioned on the first barrier layer.

公开(公告)号：US12143084B1

公开(公告)日：2024-11-12

申请号：US18302767

申请日：2023-04-18

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yu-Wei Chen

IPC: H03H11/28

Abstract: An impedance adjusting circuit and an impedance adjusting method for zero quotient (ZQ) calibration. The impedance adjusting circuit includes a reference resistor, a pull-up impedance generator, a controller and a detection circuit. The reference resistor is coupled between a sensing node and a low reference voltage. The pull-up impedance generator is coupled to an external voltage. The controller connects the pull-up impedance generator to the sensing node and compares a reference voltage and a sensing voltage on the sensing node to generate the calibration signal in a ZQ calibrating operation. When the sensing voltage is out of a specification range in the ZQ calibrating operation, the detection circuit notifies the controller to perform a compensation operation on the pull-up impedance generator, and modify the calibration signal to an adjusted calibration signal.

公开(公告)号：US12142596B2

公开(公告)日：2024-11-12

申请号：US17652487

申请日：2022-02-25

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shing-Yih Shih

IPC: H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/18

Abstract: A semiconductor structure includes an active interposer, a first stack chip module and a second stack chip module. The active interposer includes a substrate, a first control circuit located in a first control area of the substrate, a second control circuit located in a second control area of the substrate, and a communication circuit connected between the first control circuit and the second control circuit. The first stack chip module is stacked vertically on the first control area of the active interposer and the second stack chip module is stacked vertically on the second control area of the active interposer. In addition, a semiconductor structure manufacturing method is also disclosed herein.

公开(公告)号：US12142518B2

公开(公告)日：2024-11-12

申请号：US17701949

申请日：2022-03-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Wei-Chen Pan

IPC: H01L21/768 ,  H01L21/027 ,  G03F1/38

Abstract: The present application discloses a method for fabricating a semiconductor device including: providing a photomask including an opaque layer on a mask substrate and surrounding a translucent layer on the mask substrate; forming a pre-process mask layer on a device stack; patterning the pre-process mask layer using the photomask to form a patterned mask layer including a mask region corresponding to the opaque layer, a trench region corresponding to the translucent layer, and a via hole corresponding to the mask opening of via feature; performing a damascene etching process to form a via opening and a trench opening in the device stack. The device stack includes a first dielectric layer on a substrate, a first etch stop layer on the first dielectric layer, and a second dielectric layer on the first etch stop layer. The damascene etching process forms the trench opening having a bottom on the first etch stop layer.

公开(公告)号：US20240371857A1

公开(公告)日：2024-11-07

申请号：US18239859

申请日：2023-08-30

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： CHIN-LING HUANG

IPC: H01L27/02 ,  H01L23/522 ,  H01L23/525 ,  H01L23/528 ,  H01L23/64

Abstract: A semiconductor device structure includes an isolation structure disposed in a semiconductor substrate. The semiconductor device structure also includes a fuse and a resistor electrode disposed in the semiconductor substrate. The isolation structure is disposed between the fuse and the resistor electrode, and the isolation structure is closer to the resistor electrode than the fuse. The semiconductor device structure further includes a source/drain (S/D) region disposed in the semiconductor substrate and between the fuse and the isolation structure. The S/D region is electrically connected to the resistor electrode.

公开(公告)号：US20240371651A1

公开(公告)日：2024-11-07

申请号：US18142164

申请日：2023-05-02

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： TSE-YAO HUANG

IPC: H01L21/311

Abstract: A semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate, and a second dielectric layer disposed over the first dielectric layer. The semiconductor device structure also includes a first semiconductor structure disposed over the second dielectric layer. The first semiconductor structure has a first portion and a second portion separated from each other by an opening. The semiconductor device structure further includes a second semiconductor structure disposed over the second dielectric layer and in the opening. The second semiconductor structure has a first portion and a second portion separated from each other. Moreover, the first portion of the second semiconductor structure is in direct contact with the first portion of the first semiconductor structure, and the second portion of the second semiconductor structure is in direct contact with the second portion of the first semiconductor structure.