公开(公告)号：US06720577B2

公开(公告)日：2004-04-13

申请号：US09943965

申请日：2001-08-31

Applicant: Tatsuya Arao ,  Atsuo Isobe ,  Toru Takayama

Inventor： Tatsuya Arao ,  Atsuo Isobe ,  Toru Takayama

IPC: H01L2904

CPC classification number: G02F1/133305 ,  G02F1/1362 ,  G02F1/136213 ,  G02F1/136227 ,  G02F2001/136295 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3244 ,  H01L29/66742 ,  H01L29/78603

Abstract: In a semiconductor device having a substrate which has a metal surface, an insulating film which is formed on the substrate having the metal surface, and a pixel unit which is formed on the insulating film; the pixel unit includes a TFT, and wiring lines connected with the TFT, and a storage capacitor is constituted by the substrate (11) having the metal surface, the insulating film (12), and the wiring line (21). As the insulating film is thinner, and as the area of a region where the insulating film and the wiring line lie in contact is larger, the storage capacitor is endowed with a larger capacity.

Abstract translation: 在具有金属表面的基板的半导体器件中，形成在具有金属表面的基板上的绝缘膜和形成在绝缘膜上的像素单元; 像素单元包括TFT和与TFT连接的布线，并且存储电容器由具有金属表面的基板（11），绝缘膜（12）和布线（21）构成。 由于绝缘膜更薄，并且随着绝缘膜和布线接触的区域的面积较大，所以存储电容器具有较大的容量。

公开(公告)号：US06399960B1

公开(公告)日：2002-06-04

申请号：US09353370

申请日：1999-07-14

Applicant: Shunpei Yamazaki ,  Etsuko Fujimoto ,  Atsuo Isobe ,  Toru Takayama ,  Kunihiko Fukuchi

Inventor： Shunpei Yamazaki ,  Etsuko Fujimoto ,  Atsuo Isobe ,  Toru Takayama ,  Kunihiko Fukuchi

IPC: H01L3300

CPC classification number: H01L27/1237 ,  G02F1/13454 ,  H01L27/1248 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/78645

Abstract: The invention is to provide a high-productivity method for fabricating a TFT device having different LDD structures on one and the same substrate, and the TFT device. Specifically, the invention provides a novel TFT structure, and a high-productivity method for fabricating it. A Ta film or a Ta-based film having good heat resistance is used for forming interconnections, and the interconnections are covered with a protective film. The interconnections can be subjected to heat treatment at high temperatures (400 to 700° C.), and, in addition, the protective film serves as an etching stopper. In the peripheral driving circuit portion in the device, TFTs having an LDD structure are disposed in a self-aligned process in which is used side walls 126 and 127; while in the pixel matrix portion therein, TFTs having an LDD structure are disposed in a non-self-aligned process in which is used an insulator 125.

Abstract translation: 本发明提供一种用于制造在同一基板上具有不同LDD结构的TFT器件和TFT器件的高生产率方法。 具体地说，本发明提供了一种新颖的TFT结构，以及高生产率的制造方法。 使用具有良好耐热性的Ta膜或Ta基膜形成互连，并且互连用保护膜覆盖。 互连可以在高温（400〜700℃）下进行热处理，另外，保护膜用作蚀刻停止体。 在器件的外围驱动电路部分中，具有LDD结构的TFT以自对准工艺设置，其中使用侧壁126和127; 而在其中的像素矩阵部分中，具有LDD结构的TFT被设置在非自对准工艺中，其中使用绝缘体125。

公开(公告)号：US06392255B1

公开(公告)日：2002-05-21

申请号：US09671780

申请日：2000-09-27

Applicant: Hiroshi Shibata ,  Atsuo Isobe

Inventor： Hiroshi Shibata ,  Atsuo Isobe

IPC: H01L27108

CPC classification number: H01L27/1248 ,  G02F1/136213 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2201/40 ,  H01L27/124 ,  H01L27/1255

Abstract: To provide a liquid crystal display device having high quality display with a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of a capacitor wiring in a timely manner to effectively reduce the load. A scanning line is formed on a layer that is different from a gate electrode so that the capacitor wiring is arranged in parallel with a signal line. Each pixel is connected to the individually independent capacitor wiring via a dielectric. Therefore, variations in the electric potential of the capacitor wiring caused by a writing-in electric current of adjacent pixels can be avoided, thereby obtaining satisfactory display images.

Abstract translation: 为了提供具有高开口率的高质量显示的液晶显示装置，同时确保足够的存储电容器（Cs），并且同时通过将电容器布线的负载（像素写入电流）分散在 及时有效减轻负荷。 扫描线形成在与栅电极不同的层上，使得电容器布线与信号线并联布置。 每个像素通过电介质连接到单独独立的电容器布线。 因此，可以避免由相邻像素的写入电流引起的电容器布线的电位变化，从而获得令人满意的显示图像。

公开(公告)号：US09130051B2

公开(公告)日：2015-09-08

申请号：US13402212

申请日：2012-02-22

Applicant: Hideto Ohnuma ,  Atsuo Isobe ,  Hiromichi Godo

Inventor： Hideto Ohnuma ,  Atsuo Isobe ,  Hiromichi Godo

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/02

CPC classification number: H01L29/78696 ,  H01L21/0237 ,  H01L21/02675 ,  H01L21/02691 ,  H01L27/1281

Abstract: A semiconductor device having a highly responsive thin film transistor (TFT) with low subthreshold swing and suppressed decrease in the on-state current and a manufacturing method thereof are demonstrated. The TFT of the present invention is characterized by its semiconductor layer where the thickness of the source region or the drain region is larger than that of the channel formation region. Manufacture of the TFT is readily achieved by the formation of an amorphous semiconductor layer on a projection portion and a depression portion, which is followed by subjecting the melting process of the semiconductor layer, resulting in the formation of a crystalline semiconductor layer having different thicknesses. Selective addition of impurity to the thick portion of the semiconductor layer provides a semiconductor layer in which the channel formation region is thinner than the source or drain region.

Abstract translation: 示出了具有低亚阈值摆动和抑制导通电流下降的高响应性薄膜晶体管（TFT）的半导体器件及其制造方法。 本发明的TFT的特征在于其源极区域或漏极区域的厚度大于沟道形成区域的厚度的半导体层。 通过在突起部分和凹陷部分上形成非晶半导体层来容易地实现TFT的制造，随后对半导体层进行熔化处理，形成具有不同厚度的晶体半导体层。 选择性地向半导体层的厚部分添加杂质提供了沟道形成区域比源区或漏区更薄的半导体层。

公开(公告)号：US09082663B2

公开(公告)日：2015-07-14

申请号：US13608042

申请日：2012-09-10

Applicant: Atsuo Isobe ,  Toshinari Sasaki

Inventor： Atsuo Isobe ,  Toshinari Sasaki

IPC: H01L29/78 ,  H01L21/336 ,  H01L27/12 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L29/41733 ,  H01L29/78618 ,  H01L29/7869

Abstract: In a semiconductor device including an oxide semiconductor layer, a conductive layer is formed in contact with a lower portion of the oxide semiconductor layer and treatment for adding an impurity is performed, so that a channel formation region and a pair of low-resistance regions between which the channel formation region is sandwiched are formed in the oxide semiconductor layer in a self-aligned manner. Wiring layers electrically connected to the conductive layer and the low-resistance regions are provided in openings of an insulating layer.

Abstract translation: 在包括氧化物半导体层的半导体器件中，形成与氧化物半导体层的下部接触的导电层，并且进行用于添加杂质的处理，使得沟道形成区域和一对低电阻区域在 在自对准的方式在氧化物半导体层中形成夹着沟道形成区域的区域。 电连接到导电层和低电阻区域的接线层设置在绝缘层的开口中。

公开(公告)号：US08878288B2

公开(公告)日：2014-11-04

申请号：US13446026

申请日：2012-04-13

Applicant: Atsuo Isobe ,  Toshinari Sasaki

Inventor： Atsuo Isobe ,  Toshinari Sasaki

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/78603 ,  H01L29/4236 ,  H01L29/42384 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a highly reliable semiconductor device. To provide a semiconductor device which prevents a defect and achieves miniaturization. An oxide semiconductor layer in which the thickness of a region serving as a source region or a drain region is larger than the thickness of a region serving as a channel formation region is formed in contact with an insulating layer including a trench. In a transistor including the oxide semiconductor layer, variation in threshold voltage, degradation of electric characteristics, and shift to normally on can be suppressed and source resistance or drain resistance can be reduced, so that the transistor can have high reliability.

Abstract translation: 提供高度可靠的半导体器件。 提供一种防止缺陷并实现小型化的半导体器件。 形成与包括沟槽的绝缘层接触的用作源区或漏区的区域的厚度大于用作沟道形成区的区的厚度的氧化物半导体层。 在包括氧化物半导体层的晶体管中，可以抑制阈值电压的变化，电特性的劣化和正常的导通，可以降低源电阻或漏极电阻，从而晶体管可以具有高的可靠性。

公开(公告)号：US08809862B2

公开(公告)日：2014-08-19

申请号：US12909393

申请日：2010-10-21

Applicant: Tamae Takano ,  Atsuo Isobe

Inventor： Tamae Takano ,  Atsuo Isobe

IPC: H01L29/04

CPC classification number: H01L29/78606 ,  H01L27/1214 ,  H01L27/1266 ,  H01L27/13 ,  H01L29/0603 ,  H01L29/78609 ,  H01L29/78636

Abstract: The present invention provides a semiconductor device which suppresses a short circuit and a leakage current between a semiconductor film and a gate electrode generated by a break or thin thickness of a gate insulating film in an end portion of a channel region of the semiconductor film, and the manufacturing method of the semiconductor device. Plural thin film transistors which each have semiconductor film provided over a substrate continuously, conductive films provided over the semiconductor film through a gate insulating film, source and drain regions provided in the semiconductor film which are not overlapped with the conductive films, and channel regions provided in the semiconductor film existing under the conductive films and between the source and drain regions. And impurity regions provided in the semiconductor film which is not overlapped with the conductive film and provided adjacent to the source and drain regions. Further, the conductive films are provided over the channel regions and regions of the semiconductor film which are provided adjacent to the channel regions.

Abstract translation: 本发明提供一种半导体器件，其抑制由半导体膜的沟道区域的端部中的栅极绝缘膜的断裂或薄的厚度产生的半导体膜和栅电极之间的短路和漏电流，以及 半导体器件的制造方法。 连续地设置在基板上的半导体膜的多个薄膜晶体管，通过栅极绝缘膜设置在半导体膜上的导电膜，设置在半导体膜中的不与导电膜重叠的源区和漏区，以及设置的沟道区 在存在于导电膜之下以及源极和漏极区之间的半导体膜中。 以及设置在半导体膜中的不与导电膜重叠并且设置在源极和漏极区附近的杂质区。 此外，导电膜设置在与沟道区相邻设置的半导体膜的沟道区域和区域之上。

公开(公告)号：US08809853B2

公开(公告)日：2014-08-19

申请号：US13409316

申请日：2012-03-01

Applicant: Toshihiko Saito ,  Kiyoshi Kato ,  Atsuo Isobe

Inventor： Toshihiko Saito ,  Kiyoshi Kato ,  Atsuo Isobe

IPC: H01L29/78 ,  H01L29/772

CPC classification number: H01L27/0688 ,  G11C16/0433 ,  H01L21/02565 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/78 ,  H01L29/7869 ,  H01L29/78696

Abstract: With a combination of a transistor including an oxide semiconductor material and a transistor including a semiconductor material other than an oxide semiconductor, a semiconductor device with a novel structure in which data can be retained for a long time and does not have a limitation on the number of writing can be obtained. When a connection electrode for connecting the transistor including a semiconductor material other than an oxide semiconductor to the transistor including an oxide semiconductor material is smaller than an electrode of the transistor including a semiconductor material other than an oxide semiconductor that is connected to the connection electrode, the semiconductor device with a novel structure can be highly integrated and the storage capacity per unit area can be increased.

Abstract translation: 通过包括氧化物半导体材料的晶体管和包括除了氧化物半导体之外的半导体材料的晶体管的组合，具有可以长时间保持数据并且对数字没有限制的新颖结构的半导体器件 的写作可以获得。 当用于将包括氧化物半导体的半导体材料的晶体管连接到包括氧化物半导体材料的晶体管的连接电极小于包含与连接电极连接的氧化物半导体以外的半导体材料的晶体管的电极时， 具有新颖结构的半导体器件可以高度集成，并且可以增加每单位面积的存储容量。

公开(公告)号：US08530333B2

公开(公告)日：2013-09-10

申请号：US12721298

申请日：2010-03-10

Applicant: Atsuo Isobe ,  Hiromichi Godo ,  Satoshi Shinohara

Inventor： Atsuo Isobe ,  Hiromichi Godo ,  Satoshi Shinohara

IPC: H01L21/46

CPC classification number: H01L21/76254 ,  H01L21/02532 ,  H01L21/02675 ,  H01L27/1218 ,  H01L29/66772

Abstract: An object is to provide a semiconductor device which solves a problem that can occur when a substrate having an insulating surface is used. The semiconductor device includes a base substrate having an insulating surface; a conductive layer over the insulating surface; an insulating layer over the conductive layer; a semiconductor layer having a channel formation region, a first impurity region, a second impurity region, and a third impurity region provided between the channel formation region and the second impurity region over the insulating layer; a gate insulating layer configured to cover the semiconductor layer; a gate electrode over the gate insulating layer; a first electrode electrically connected to the first impurity region; and a second electrode electrically connected to the second impurity region. The conductive layer is held at a given potential.

Abstract translation: 本发明的目的是提供一种半导体器件，其解决了当使用具有绝缘表面的衬底时可能发生的问题。 半导体器件包括具有绝缘表面的基底衬底; 绝缘表面上的导电层; 导电层上的绝缘层; 绝缘层上设置有沟道形成区域和第二杂质区域之间的具有沟道形成区域，第一杂质区域，第二杂质区域和第三杂质区域的半导体层; 构造成覆盖半导体层的栅极绝缘层; 栅绝缘层上的栅电极; 电连接到第一杂质区的第一电极; 和与第二杂质区电连接的第二电极。 导电层保持在给定的电位。

公开(公告)号：US20110298027A1

公开(公告)日：2011-12-08

申请号：US13115239

申请日：2011-05-25

Applicant: Atsuo Isobe ,  Yoshinori Ieda ,  Kiyoshi Kato ,  Yuto Yakubo ,  Yuki Hata

Inventor： Atsuo Isobe ,  Yoshinori Ieda ,  Kiyoshi Kato ,  Yuto Yakubo ,  Yuki Hata

IPC: H01L27/108 ,  H01L27/088 ,  H01L21/336

CPC classification number: H01L27/10852 ,  G11C16/0433 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/1225

Abstract: It is an object to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limitation on the number of writings. A semiconductor device includes a second transistor and a capacitor provided over a first transistor. A source electrode of the second transistor which is in contact with a gate electrode of the first transistor is formed using a material having etching selectivity with respect to the gate electrode. By forming the source electrode of the second transistor using a material having etching selectivity with respect to the gate electrode of the first transistor, a margin in layout can be reduced, so that the degree of integration of the semiconductor device can be increased.

Abstract translation: 本发明的目的是提供一种具有新颖结构的半导体器件，其中即使在不提供电力的情况下也可以保持存储的数据，并且对写入数量没有限制。 半导体器件包括设置在第一晶体管上的第二晶体管和电容器。 使用具有相对于栅电极的蚀刻选择性的材料形成与第一晶体管的栅电极接触的第二晶体管的源电极。 通过使用相对于第一晶体管的栅电极具有蚀刻选择性的材料形成第二晶体管的源电极，可以减小布局的裕度，从而可以提高半导体器件的集成度。